Topology Design of Extended Torus and Ring for Low Latency Network-on-Chip Architecture

Ng Yen Phing (University Malaysia Perlis)
M. N. Mohd Warip (University Malaysia Perlis)
Phaklen Ehkan (University Malaysia Perlis)
F. W. Zulkefli (University Malaysia Perlis)
R. Badlishah Ahmad (University Malaysia Perlis)

TELKOMNIKA (Telecommunication Computing Electronics and Control)
Vol 15, No 2: June 2017

In essence, Network-on-Chip (NoC) also known as on-chip interconnection network has been proposed as a design solution to System-on-Chip (SoC). The routing algorithm, topology and switching technique are significant because of the most influential effect on the overall performance of Network-on-Chip (NoC). Designing of large scale topology alongside the support of deadlock free, low latency, high throughput and low power consumption is notably challenging in particular with expanding network size. This paper proposed an 8x8 XX-Torus and 64 nodes XX-Ring topology schemes for Network-on-Chip to minimize the latency by decrease the node diameter from the source node to destination node. Correspondingly, we compare in differences on the performance of mesh, full-mesh, torus and ring topologies with XX-Torus and XX-Ring topologies in term of latency. Results show that XX-Ring outperforms the conventional topologies in term of latency. XX-Ring decreases the average latency by 106.28%, 14.80%, 6.7 1%, 1.73%, 442.24% over the mesh, fully-mesh, torus, XX-torus, and Ring topologies.