Pre-processing Block Hardware Architecture in Image Processing using Reconfigurable Platform

G N, Chiranjeevi

Computer Science and Information Technologies
List of Accepted Papers (with minor revisions)

Real time image processing is a challenging task in which fetching the sub image requires offset memory access apart from core processing needs. This paper aims at overcoming the offset needs for memory addressing in pre-processing blocks. Another feature of this present work is to appending the image data with customized algorithmic requiments viz duplicating, zero padding. For K x K kernel size, the proposed hardware architecture can be programmed to fetch K pixels in one cycle, reducing the data access time. Results have been compared with software based processing for K x K spatial filtering. performance indicates significant timing improvement using proposed pre-processing hardware block