Design of the Digital I/O Pad Buffer for Mixed-Voltage Application

Said El Mouzouade (Laboratory of Computer Science and Interdisciplinary Physics (L.I.P.I), Normal Superior School Fez (ENSF) Sidi Mohamed Ben Abdellah University, Fez, Morocco)
Karim El khadiri (Laboratory of Computer Science and Interdisciplinary Physics (L.I.P.I), Normal Superior School Fez (ENSF) Sidi Mohamed Ben Abdellah University, Fez, Morocco)
Zakia Lakhliai (Laboratory of Computer Science and Interdisciplinary Physics (L.I.P.I), Normal Superior School Fez (ENSF) Sidi Mohamed Ben Abdellah University, Fez, Morocco)
Ahmed Tahiri (Laboratory of Computer Science and Interdisciplinary Physics (L.I.P.I), Normal Superior School Fez (ENSF) Sidi Mohamed Ben Abdellah University, Fez, Morocco)

Indonesian Journal of Electrical Engineering and Informatics (IJEEI)
Vol 9, No 1: March 2021

A new circuit design of digital bidirectional input/output (I/O) pad buffer for mixed voltage is presented. The digictal bidirectional I/0 buffer is designed to avoid reflections by matching the output impedance to the 50 ohms of the transmission line and having overshoots and undershoots below 300mV by increasing the output impedance. The digital bidirectional I/O pad buffer provides minimum delays between input and output and minimum rising and falling times. The proposed digital bidirectional I/O pad buffer was designed, simulated and layouted in Cadence using in TSMC  0.18um CMOS process with a linear resistive element electrically connected at an I/O pad for limiting a processed data I/O signal. The output rising time and falling time are 0.42 ns and 0.93 ns with 3pF load respectively. The final chip area is only 5 um2 .