TELKOMNIKA (Telecommunication Computing Electronics and Control)
Vol 19, No 6: December 2021

Performance improvement of fractional N-PLL synthesizers for digital communication applications

Nour Zaid Naktal (Ninevah University)
A. Z. Yonis (Ninevah University)
Khalid Khalil Mohammed (Ninevah University)



Article Info

Publish Date
01 Dec 2021

Abstract

Loop filter with two order was designed to improve the performance of the fractional N-phase locked loop (PLL) circuit (reference spurs noise and switching time), decreasing these two factors give good characteristic to fractional N-PLL circuit, the second order and third order loop filters are widely used in frequency synthesizer because they give good stability tolerance and for their simple architecture. They are designed at bandwidth B=125 KHz and its multipoles, at two values of the phase margin (pm)= 35°, 57°. MATLAB program was used to find the lock time, the component values for each element in the loop filter, also the filter impedance T(s), the bode plot of frequency response for close loop (CL) and open loop gain (OL). It is found by comparing the result of the frequency response for the 2nd order loop filter and 3rd order loop filter, that increasing the order of the filter will reduce the spurs noise that destroy the received signal at receiving side.

Copyrights © 2021






Journal Info

Abbrev

TELKOMNIKA

Publisher

Subject

Computer Science & IT

Description

Submitted papers are evaluated by anonymous referees by single blind peer review for contribution, originality, relevance, and presentation. The Editor shall inform you of the results of the review as soon as possible, hopefully in 10 weeks. Please notice that because of the great number of ...