<![CDATA[Design for testability (DFT) is a technique, which facilitates a design to become testable after fabrication. As the technology node is shrinking, complexity of the system-on-chip (SoC) becomes high and inserting DFT and verifying its timing becomes complex. For these complex SoC, generating DFT timing constraints becomes difficult in shift mode and the time required for the generation of these timing constraints is also more. A new methodology proposed to overcome these issues. The main objective of this work is to propose the flow for generating DFT timing constraints for the complex SoC in shift mode, by dividing the design blocks into scan blocks and non-scan blocks. To target the whole design without getting all paths reported, relaxation of the setup, and hold time for non-scan blocks plays crucial role. If not, the time taken to generate DFT timing constraints would be more. Implemented methodology of this paper includes design setup, timing exceptions, and synopsys design constraints (SDC) generation for DFT timing. Design setup consists of all pre-requisites for design such as netlists, timing libraries, and exceptions. Synopsys primetime (PT Shell) is used for all the timing-related checks. Compared to conventional methods, the proposed flow reduces the overall time by 40% to generate constraints.]]>
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