<![CDATA[Block cipher algorithms are crucial for securing applications on resource-constrained devices. This paper introduces the modified light encryption device (MLED) cipher-decipher architecture, specifically designed to accommodate both 64-bit and 128-bit key sizes while maintaining a consistent 64-bit block and data size. MLED comprises 8-step and 12-step processes for MLED-64 and MLED-128 modules, respectively. Each stage involves a four-round operation followed by an add-round key operation. The add constant module (ACM) and mixed column modules (MCMs) within the round operation have been optimized for improved latency and throughput. Performance analysis reveals that MLED-64/128 requires less than 1% of the available slices and operates at 125 MHz on the Artix-7 FPGA. It achieves delays of 7.5 and 12.5 clock cycles for MLED-64 and MLED-128, respectively, translating to throughputs of 1366.5 Mbps and 819.89 Mbps. Additionally, MLED-64/128 exhibits hardware efficiencies of 2.373 and 0.986 Mbps/slice, respectively. Comparative evaluations with existing LED and other block ciphers (BCs) demonstrate that MLED-64/128 achieves significant improvements in latency, throughput, and efficiency, making it a compelling choice for securing resource-constrained IoT applications.]]>
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