<![CDATA[Cache memory in microprocessors has an important role in improving computer system performance by reducing data access time. This research aims to test the hypothesis that increasing the size and level of cache memory can significantly improve microprocessor performance. The research methodology involves a literature study on the concept of cache memory and experimental simulations using computer architecture simulators, such as Gem5, to model scenarios with varying cache sizes and levels. In these simulations, performance parameters such as memory access latency, throughput, and Instructions Per Cycle (IPC) were measured and analyzed. The results show that increasing cache size and level generally contributes towards improving microprocessor performance by reducing data access time. Further statistical analysis supports the hypothesis that there is a positive correlation between cache size and level and system efficiency. These findings provide useful insights in future microprocessor architecture design and memory system optimization.]]>
Copyrights © 2024
