<![CDATA[The Fast Fourier Transform (FFT) is widely used in digital signal processing ap-plications and particularly for implementing convolution operation for real-time object detection using CNN. This paper proposes an efficient hardware architecture for Radix-2 FFT computation, implemented on an FPGA, employing multiple parallel and pipelined stages of butterfly units. The proposed architecture utilises Block RAM to store inputs and twiddle factor values to compute the transform. The hardware for the proposed architecture is synthesised on a Zync Ultrascale FPGA and its performance is evaluated using parameters such as critical path delay, throughput, device utilisation and power consumption.The performance of the proposed parallel pipelined architecture for 8 point FFT, measured in FFTOPS, is found to be 67% higher than the non-pipelined architecture. Performance comparison with the state-of-the-art parallel pipelined methods confirm the acceleration achieved by the proposed FFT architecture. A comprehensive comparison of the proposed hardware with the synthesised version of the FFT IP core bundled with the Vivado Design suite is also presented in the paper.]]>
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