A Survey of Fault-Injection Methodologies for Soft Error Rate Modeling in Systems-on-Chips

Yeong Seob Jeong (Seoul National University of Science and Technology 202 Changhak Hall)
Seong Mo Lee (Seoul National University of Science and Technology)
Seung Eun Lee (Seoul National University of Science and Technology 202 Changhak Hall)

Bulletin of Electrical Engineering and Informatics
Vol 5, No 2: June 2016

The development of process technology has increased system performance, but the system failure probability has also significantly increased. It is important to consider the system reliability in addition to the cost, performance, and power consumption. In this paper, we describe the types of faults that occur in a system and where these faults originate. Then, fault-injection techniques, which are used to characterize the fault rate of a system-on-chip (SoC), are investigated to provide a guideline to SoC designers for the realization of resilient SoCs.