<![CDATA[Arrhythmia classification is categorization of irregular heart rhythms depending on patterns detected in electrocardiogram (ECG) signals assist in treatment and diagnosis of cardiac conditions. ECG evaluates heart’s electrical activity to diagnose various heart conditions, but it is affected by interference or noise. ECG’s signal filtering is essential pre-processing stage that minimizes noise and highlights wave characteristics in ECG data. However, digital filters are normally constructed by multiplying coefficient and then multiplying value given as feedback which leads to more power and area consumption. To solve these issues, coefficient memory compression (CMC) technique is proposed with an adaptive FIR filter (AFF) to achieve low area and low power dissipation by compressing memory requirements in a field programmable gate array (FPGA). An adaptive FIR filter is employed to effectively minimize noise like baseline noise, muscle contraction noise, and low-frequency noise. The performance of CMC-AFF is analyzed in terms of look up table (LUT), register, digital signal processing (DSP), power, and global buffer (BufG). The proposed approach achieves a low power consumption of 0.012 W in Zed Board Zynq7000 AP system on chip (SoC) FPGA device compared to existing techniques like collateral and sequence approaches using Bartlet filter and low-power ECG processor using Bartlet filter respectively.]]>
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