Modification of Sigma-Delta DAC for Digital Spike Signal Processing

Dewanto, Muhammad Ridho
Hizbullah, Mohammad Naufal
Sugiarto, Kharis

SNTE
Vol. 4 No. 1 (2025): SNTE III

his study aims to modify the architecture of a Sigma-Delta Digital-to-Analog Converter (DAC) based on FPGA to support the conversion of digital spike signals to analog in neuromorphic systems. The main focus of the modification lies in increasing the order of the noise loop filter and implementing a Multi-Stage Noise Shaping (MASH) structure consisting of a combination of 1-bit and 3-bit DACs. The modification process was carried out in the truncation and feedback stages and simulated using the Verilog programming language on the Altera Cyclone V FPGA. Evaluation was conducted using tonic spike inputs representing a 15 Hz sinusoidal signal. The results show improvements in the linearity of the analog output signal, enhancement of quality parameters such as SNR and ENOB, and reduced latency. Nevertheless, some challenges remain related to truncation errors that have not been fully addressed.