<![CDATA[The increasing deployment of artificial intelligence (AI) in real-time and edge applications intensified the demand for energy-efficient hardware capable of high-throughput processing. Conventional digital processors were constrained by sequential data processing, memory bandwidth limitations, and high-power consumption, making them suboptimal for edge-based AI. This review presented a comprehensive analysis of analog very-large-scale integration (VLSI) design approaches for neural network (NN) implementation focusing on circuit-level architectures including in-memory analog computing, current-mode circuits, switched-capacitor (SC) techniques, and operational transconductance amplifier (OTA)-based designs. Significant hardware design considerations such as process variation, crossbar scalability, precision–linearity trade-offs, and mixed-signal interface challenges were critically examined. Furthermore, training methodologies—spanning offline learning, circuit calibration, and programmability were discussed in the context of analog AI hardware. The review incorporated case studies, recent developments in edge deployment, and a comparative analysis of advanced analog VLSI chips. Key performance evaluation metrics such as accuracy, calibration overhead, noise robustness, and energy per inference, were also addressed. Circuit-level design aspects that impacted the performance, precision, and reliability of analog computing blocks were discussed. The paper concluded by identifying research gaps and future directions for the development of analog AI hardware suitable for real-world edge applications.]]>
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