Design of 15 level reduced switches inverter topology using multicarrier sinusoidal pulse width modulation

Selvabharathi Devadoss (SRM Institute of Science and Technology)
Palanisamy Ramasamy (SRM Institute of Science and Technology)
Amit Amit (SRM Institute of Science and Technology)
Aditya Agarwal (SRM Institute of Science and Technology)
Saptarshi Gupta (SRM Institute of Science and Technology)

TELKOMNIKA (Telecommunication Computing Electronics and Control)
Vol 21, No 1: February 2023

In this proposed paper, multicarrier sinusoidal pulse width modulation (M-SPWM) method is implemented for design of 15 level reduced switches inverter topology. This inverter topology generates 15 level output-voltage with suitable switching pulse production using M-SPWM and altered level of voltages are attained with distinction of modulation index. The split inductor is used to diminish the harmonic content and flatted output current. This type of system which contains different range of different range of voltage supplies. As a result, this inverter reduces the difficulty in gating time calculation and there is no neutral point fluctuation issue. This paper illuminates the modes of switching and minimization of stress in voltage and harmonic diminution are examined. The grades of the projected multilevel inverter (MLI) system are verified using Matlab/Simulink and dsPIC controller respectively