Design and analysis of low-k dielectric TSV liners for noise mitigation in high-frequency 3D ICs

Pathakunta Guru Prathap Reddy (Bharatiya Engineering Science and Technology Innovation University)
Sravan Abhilash Kothapalli (Mallareddy University)

International Journal of Informatics and Communication Technology (IJ-ICT)
Vol 15, No 3: September 2026

Moore’s Law has driven the development of very large-scale integration (VLSI) technology, allowing continuous transistor scaling to increase speed, density, and performance. However, as two-dimensional (2D) integrated circuits (ICs) near their physical and performance boundaries, and 2.5D ICs still face interconnect delay and power issues, three-dimensional (3D) integration has become a practical solution. In 3D ICs, multiple active layers are vertically stacked and connected via through-silicon vias (TSVs), providing short, high-bandwidth interconnects between layers. Electrical TSVs are essential for signal transmission, but also cause noise coupling between adjacent TSVs, where an aggressive TSV can induce interference in a nearby TSV. This coupling can impair signal integrity, increasing delay and power consumption. To mitigate this, low-dielectric-constant (low-k) materials are used to reduce capacitive coupling. In this study, materials such as benzocyclobutene (BCB), Perylene-N, and Teflon AF 1600 are compared with conventional SiO₂. Generally, TSVs are two structures — single-liner and stacked-liner — which are analysed at 10 GHz and 1 THz frequencies. At 10 GHz, the single-liner structure incorporating SiO₂ exhibits a noise reduction of about 6.56 dB, whereas the stacked-liner configuration using Teflon AF 1600 provides a noticeably greater reduction of 8.40 dB. As the operating frequency increases to 1 THz, the advantage of the low-k dielectric becomes more evident, yielding 9.63 dB noise reduction for the single-liner and 12.04 dB for the stacked-liner structure. These results indicate that low-k materials effectively suppress capacitive coupling and mitigate high-frequency interference in 3D ICs. The stacked-liner design contributes additional isolation by creating a secondary dielectric barrier, which further minimizes electric field interaction between neighboring interconnects. Thus, the integration of low-k dielectrics with optimized liner architectures significantly enhances signal integrity and overall electromagnetic performance in advanced high-frequency 3D IC systems.