<![CDATA[The continued scaling of semiconductor devices has exposed the limitations of traditional two-dimensional (2D) integrated circuit architectures. To address performance bottlenecks and interconnect constraints, the industry is increasingly adopting three-dimensional (3D) integration technologies. through-silicon vias (TSVs) are a fundamental enabler of this advancement, facilitating vertical signal transmission between stacked silicon layers. Despite their benefits, TSVs face critical challenges related to crosstalk, power dissipation, and signal delay issues that are especially pronounced in dense via arrays. This research explores the use of multi-walled carbon nanotube (MWCNT) based TSVs insulated with different dielectric liners, including silicon dioxide (SiO₂), PPC, polyimide, and benzocyclobutene (BCB). HSPICE simulations are used to evaluate crosstalk noise, power dissipation, power delay product (PDP), and energy delay product (EDP) across varying TSV pitches. Among the materials studied, BCB demonstrates the most promising results. Specifically, MWCNT TSVs with BCB at a 10,000 μm pitch achieve up to 58% reduction in functional crosstalk, 75% in dynamic crosstalk, 78% in power dissipation, and a 52% improvement in PDP compared to single-walled CNT (SWCNT) based TSVs. These findings confirm the suitability of combining MWCNT cores with low-k BCB liners for enhancing performance, energy efficiency, and signal reliability in advanced 3D integrated circuits.]]>
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