<![CDATA[As the need for highly advanced chip technology and high-performance computing grows, semiconductor technology must develop rapidly. Also, as VLSI circuits become more complex, it is more difficult and time-consuming to test circuits using traditional test methods. Hence, Chip design, verification, and testing become extremely complex and critical processes. To confirm the chip as fault-free, testing examines its functionality, timing, and connectivity. Various automatic test pattern generation (ATPG) tools have been available for a long time for fault detection. For large combinational circuits, a lot of computing resources and more time are required to use such tools. To tackle this challenge, machine learning (ML) techniques have recently been introduced as a promising alternative to improve the efficiency of test generation. Machine learning has advanced dramatically over the last few years, and it currently plays an important role in enhancing automation, efficiency, and decision-making in a variety of domains. The main purpose of this work is to explore the possibility of using machine learning to predict test vectors in digital combinational circuits and achieve comparable fault coverage. The Random Forest Regressor method is utilized for generating test vectors. Experimental results showcase that this method performs well compared to traditional tools like ATALANTA on most ISCAS85 benchmark circuits. This approach reduced test pattern generation time to 0.0146 sec, while the standard tool requires 0.02 sec for test set generation, retaining almost similar fault coverage. This research demonstrated the highest fault coverage of 96.523 for the c5315_13 circuit and the lowest coverage of 60.404 for c1908_23, compared to the ATALANTA Tool. The results demonstrate that machine learning is a promising complementary testing method for conventional ATPG tools in VLSI testing.]]>
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