<![CDATA[Advances in real-time speech recognition have led to an increasing demand for compact as well as energy-efficient MFCC hardware capable of generating accurate and consistent speech features with low computational latency. Conventional MFCC solutions frequently necessitate specialized processing resources and several math operations, resulting in increased size, power consumption, and hardware complexity. To address these restrictions, this paper proposes a modified MFCC architecture that incorporates dual window operation, a Radix-2 Time Division Multiplexed FFT (TDM FFT), and an Approximate Radix-4 Distributed Arithmetic (DA) multiplier. The proposed framework utilizes shared computational abilities for speech framing, dual window operations, FFT calculation, magnitude prediction, Mel filter bank analysis, logarithmic conversion, as well as MFCC coefficient generation. A Xilinx KV260 Zynq UltraScale+ FPGA is used to implement the standard architecture, and 45 nm CMOS ASIC synthesis is used for further assessment. The MFCC coefficients produced by MATLAB are compared with the appropriate Verilog outputs to perform functional validation. In comparison to the standard architecture, experimental results show a 50% reduction in LUT/ALM utilization, a 60% reduction in DSP resource usage, and a 45% reduction in power consumption. ASIC synthesis achieves a roughly 50% reduction in core silicon area while further reducing processing latency from 1024 to 320 clock cycles, or a 69% reduction. Time-division multiplexing, approximate distributed arithmetic processing, and efficient computing resource sharing all contribute to these gains. The findings show that the suggested architecture strikes a good balance among MFCC feature characteristics, processing speed, power consumption, as well as hardware efficiency. Thus, for low-power, low-latency, along with resource constrained real-time voice recognition applications, the proposed architecture offers a feasible and scalable approach.]]>
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