International Journal of Electrical and Computer Engineering
International Journal of Electrical and Computer Engineering (IJECE, ISSN: 2088-8708, a SCOPUS indexed Journal, SNIP: 1.001; SJR: 0.296; CiteScore: 0.99; SJR & CiteScore Q2 on both of the Electrical & Electronics Engineering, and Computer Science) is the official publication of the Institute of Advanced Engineering and Science (IAES). The journal is open to submission from scholars and experts in the wide areas of electrical, electronics, instrumentation, control, telecommunication and computer engineering from the global world.
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A framework for IoT-enabled environment aware traffic management
Mohamed Firdhous, Mohamed Fazil;
Sudantha, B. H.;
Hussien, Naseer Ali
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 1: February 2021
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/ijece.v11i1.pp518-527
Vehicular traffic has increased across all over the world especially in urban areas due to many reasons including the reduction in the cost of vehicles, degradation of the quality of public transport services and increased wealth of people. The traffic congestion created by these vehicles causes many problems. Increased environment pollution is one of the most serious negative effects of traffic congestion. Noxious gases and fine particles emitted by vehicles affect people in different ways depending on their age and present health conditions. Professionals and policy makers have devised schemes for better managing traffic in congested areas. These schemes suffer from many shortcomings including the inability to adapt to dynamic changes of traffic patterns. With the development of technology, new applications like Google maps help drivers to select less congested routes. But, the identification of the best route takes only the present traffic condition on different road segments presently. In this paper the authors propose a system that helps drivers select routes based on the present and expected environment pollution levels at critical points in a given area.
Computational and experimental study of air-core HTS transformer electrothermal behaviour at current limiting mode
Manusov, V. Z.;
Kriukov, D. O.;
Semenov, A. V.
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 1: February 2021
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/ijece.v11i1.pp155-162
The paper provides the results of the experimental and computational study of the processes occurring in high temperature superconducting transformer windings while secondary winding is short-circuited. The obtained mathematical simulation matches closely with the experimental results. The temperature variation curves for superconducting windings were analysed, and conclusions were made on the necessity of changes in HTS transformer design, namely the necessity of windings heat-insulation from each other and adding a high-resistance coating material for HTS wire in HTS transformer primary winding.
FPGA configuration of an alloyed correlated branch predictor used with RISC processor for educational purposes
Mahmood, Hadeel SH.
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 1: February 2021
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/ijece.v11i1.pp265-271
Instructions pipelining is one of the most outstanding techniques used in improving processor speed; nonetheless, these pipelined stages are constantly facing stalls that caused by nested conditional branches. During the execution of nested conditional branches, the behavior of the running branch depends on the history information of the previous ones; therefore, these branches have the greatest effect in reducing the prediction accuracy of a branch predictor among conditional branches. The purpose of this research is to reduce the stall cycles caused by correlated branches misprediction by introducing a hardware model of a branch predictor that combines both local and global prediction techniques. This predictor integrates the prediction characteristics of the alloyed predictor with those of the correlated predictor. the predictor design which implemented in VHDL (Very high-speed IC hardware description language) was inserted in previously designed MIPS (microprocessor without interlocked pipelined stages) processor and its prediction accuracy was confirmed by executing a program using the selection sort algorithm to sort 100 input numbers of different combinations ascendingly.
Simulation of a microgrid for a non-interconnected zone that integrates renewable energies
Reina, German;
Mauledoux, Mauricio;
Aviles, Oscar A.
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 1: February 2021
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/ijece.v11i1.pp201-216
This paper develops a simulation of a small electrical network (Microgid) that integrates renewable energies, the model of the micro network is made up of a solar energy source, a wind energy source, an energy storage element, a non-renewable source such as a diesel generator. The model of the microgrid represent a non-interconnected area from the electrical network in Colombia. The non-interconnected areas sometimes depend on unreliable connections to the grid integration of renewable energies could be the best option to guarantee energy in these sectors and allow generating projects with social impact. A possible solution to this deficit of energy is to supplement the production of energy with renewable energy plants from resources as sun or wind. The simulated model allowed to study the effects of the network in island mode and in interconnected mode, showing the imbalances that can be obtained by integrating renewable energies and storage systems. It is verified that with an inclusion of more than 30% of power in renewable energies there is the possibility of having load imbalances, which affect the frequency and cause instability in the network. It also verifies how a control system can regulate the load balance but must interact with the other energy sources.
DTC based on SVM for induction motor sensorless drive with fuzzy sliding mode speed controller
Massoum, Sarra;
Meroufel, Abdelkader;
Massoum, Ahmed;
Patrice, Wira
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 1: February 2021
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/ijece.v11i1.pp171-181
By using the direct torque control (DTC), robust response in ac drives can be produced. Ripples of currents, torque and flux are oberved in steady state. space vector modulation (SVM) applied in DTC and used for a sensorless induction motor (IM) with fuzzy sliding mode speed controller (FSMSC) is studied in this paper. This control can minimize the torque, flux, current and speed pulsations in steady state. To estimate the rotor speed and stator flux the model reference adaptive system (MRAS) is used that is designed from identified voltages and currents. The FSMSC is used to enhance the efficiency and the robustness of the presented system. The DTC transient advantage are maintained, while better quality steady-state performance is produced in sensorless implementation for a wide speed range. The drive system performances have been checked by using Matlab Simultaion, and successful results have been obtained. It is deduced that the proposed control system produces better results than the classical DTC.
System uncertainties estimation based adaptive robust backstepping control for DC DC buck converter
Mary, Ali Hussien;
Miry, Abbas Hussien;
Miry, Mohammed Hussein
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 1: February 2021
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/ijece.v11i1.pp347-355
This paper proposed a novel adaptive robust backstepping control scheme for DC-DC buck converter subjected to external disturbance and system uncertainty. Uncertainty in the load resistance and the input voltage represent the big challenge in buck converter control. In this work, an adaptive estimator for matched and mismatched uncertainties based backstepping control is applied for DC-DC buck converter. The updating laws are determined based on the lyapunov theorem. Thus, the difference between the estimated parameters and actual parameters converges to zero. The proposed control method is compared with the conventional sliding mode control and integral sliding mode control. Simulation results demonstrate the effectiveness and robustness of the proposed controller.
Robust adaptive controller for wheel mobile robot with disturbances and wheel slips
Vu, Nga Thi-Thuy;
Ong, Loc Xuan;
Trinh, Nam Hai;
Huong Pham, Sen Thi
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 1: February 2021
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/ijece.v11i1.pp336-346
In this paper an observer based adaptive control algorithm is built for wheel mobile robot (WMR) with considering the system uncertainties, input disturbances, and wheel slips. Firstly, the model of the kinematic and dynamic loops is shown with presence of the disturbances and system uncertainties. Next, the adaptive controller for nonlinear mismatched disturbance systems based on the disturbances observer is presented in detail. The controller includes two parts, the first one is for the stability purpose and the later is for the disturbances compensation. After that this control scheme is applied for both two loops of the system. In this paper, the stability of the closed system which consists of two control loops and the convergence of the observers is mathematically analysed based on the Lyapunov theory. Moreover, the proposed model does not require the complex calculation so it is easy for the implementation. Finally, the simulation model is built for presented method and the existed one to verify the correctness and the effectiveness of the proposed scheme. The simulation results show that the introduced controller gives the good performances even that the desired trajectory is complicated and the working condition is hard.
Text documents clustering using data mining techniques
Jalal, Ahmed Adeeb;
Ali, Basheer Husham
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 1: February 2021
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/ijece.v11i1.pp664-670
Increasing progress in numerous research fields and information technologies, led to an increase in the publication of research papers. Therefore, researchers take a lot of time to find interesting research papers that are close to their field of specialization. Consequently, in this paper we have proposed documents classification approach that can cluster the text documents of research papers into the meaningful categories in which contain a similar scientific field. Our presented approach based on essential focus and scopes of the target categories, where each of these categories includes many topics. Accordingly, we extract word tokens from these topics that relate to a specific category, separately. The frequency of word tokens in documents impacts on weight of document that calculated by using a numerical statistic of term frequency-inverse document frequency (TF-IDF). The proposed approach uses title, abstract, and keywords of the paper, in addition to the categories topics to perform the classification process. Subsequently, documents are classified and clustered into the primary categories based on the highest measure of cosine similarity between category weight and documents weights.
An area efficient memory-less ROM design architecture for direct digital frequency synthesizer
Alkurwy, Salah;
Ali, Sawal H.;
Islam, Md. Shabiul;
Idros, Faizul
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 1: February 2021
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/ijece.v11i1.pp257-264
This paper introduces a new technique of designing a read-only memory (ROM) circuit, namely; memory-less ROM as a novel approach to designing the ROM lookup table (LUT) circuit for use in a direct digital frequency synthesizer (DDFS). The proposed DDFS design uses the pipelined phase accumulator (PA) based on the kogge-stone (KS) adder. Verilog HDL programming is encoded on the architecture circuit of pipelined PA and contrasted with other PA based on various adders. The obtained results define the KS adder as having good capabilities for improving the throughput. In addition to the quarter symmetry technique, the built memory-less ROM to obtain the quarter sine amplitude waveform is proposed and implemented in the DDFS system. The implementation of the proposed technique replaces the necessary ROM registers (384 D flip-flops) and multiplexers with simple logic gate circuits instead of traditional ROMs. This technique would reduce the area size and cell count by 56% and 32.6% respectively.
An area efficient memory-less ROM design architecture for direct digital frequency synthesizer
Alkurwy, Salah;
Ali, Sawal H.;
Islam, Md. Shabiul;
Idros, Faizul
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 1: February 2021
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/ijece.v11i1.pp257-264
This paper introduces a new technique of designing a read-only memory (ROM) circuit, namely; memory-less ROM as a novel approach to designing the ROM lookup table (LUT) circuit for use in a direct digital frequency synthesizer (DDFS). The proposed DDFS design uses the pipelined phase accumulator (PA) based on the kogge-stone (KS) adder. Verilog HDL programming is encoded on the architecture circuit of pipelined PA and contrasted with other PA based on various adders. The obtained results define the KS adder as having good capabilities for improving the throughput. In addition to the quarter symmetry technique, the built memory-less ROM to obtain the quarter sine amplitude waveform is proposed and implemented in the DDFS system. The implementation of the proposed technique replaces the necessary ROM registers (384 D flip-flops) and multiplexers with simple logic gate circuits instead of traditional ROMs. This technique would reduce the area size and cell count by 56% and 32.6% respectively.