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International Journal of Electrical and Computer Engineering

IJECE
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Published by Institute of Advanced Engineering and Science

ISSN : 20888708 EISSN : 27222578 DOI : -

Core Subject : Science, Engineering,

Computer Science & IT Electrical & Electronics Engineering

International Journal of Electrical and Computer Engineering (IJECE, ISSN: 2088-8708, a SCOPUS indexed Journal, SNIP: 1.001; SJR: 0.296; CiteScore: 0.99; SJR & CiteScore Q2 on both of the Electrical & Electronics Engineering, and Computer Science) is the official publication of the Institute of Advanced Engineering and Science (IAES). The journal is open to submission from scholars and experts in the wide areas of electrical, electronics, instrumentation, control, telecommunication and computer engineering from the global world.

Arjuna Subject : Ilmu Komputer (semua kategori) - Ilmu Komputer (Lain-Lain)

Articles 151 Documents

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Search results for , issue "Vol 8, No 6: December 2018" : 151 Documents clear

Deep Belief Networks for Recognizing Handwriting Captured by Leap Motion Controller Abas Setiawan; Reza Pulungan
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 6: December 2018
Publisher : Institute of Advanced Engineering and Science

Leap Motion controller is an input device that can track hands and fingers position quickly and precisely. In some gaming environment, a need may arise to capture letters written in the air by Leap Motion, which cannot be directly done right now. In this paper, we propose an approach to capture and recognize which letter has been drawn by the user with Leap Motion. This approach is based on Deep Belief Networks (DBN) with Resilient Backpropagation (Rprop) fine-tuning. To assess the performance of our proposed approach, we conduct experiments involving 30,000 samples of handwritten capital letters, 8,000 of which are to be recognized. Our experiments indicate that DBN with Rprop achieves an accuracy of 99.71%, which is better than DBN with Backpropagation or Multi-Layer Perceptron (MLP), either with Backpropagation or with Rprop. Our experiments also show that Rprop makes the process of fine-tuning significantly faster and results in a much more accurate recognition compared to ordinary Backpropagation. The time needed to recognize a letter is in the order of 5,000 microseconds, which is excellent even for online gaming experience.

Novel Bacteria Foraging Optimization for Energy-efficient Communication in Wireless Sensor Network Hemavathi P; Nandakumar A. N.
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 6: December 2018
Publisher : Institute of Advanced Engineering and Science

Optimization techniques based on Swarm-intelligence has been reported to have significant benefits towards addressing communication issues in Wireless Sensor Network (WSN). We reviewed the most dominant swarm intelligence technique called as Bacteria Foraging Optimization (BFO) to find that there are very less significant model towards addressing the problems in WSN. Therefore, the proposed paper introduced a novel BFO algorithm which maintains a very good balance between the computational and communication demands of a sensor node unlike the conventional BFO algorithms. The significant contribution of the proposed study is to minimize the iterative steps and inclusion of minimization of both receiving / transmittance power in entire data aggregation process. The study outcome when compared with standard energy-efficient algorithm was found to offer superior network lifetime in terms of higher residual energy as well as data transmission performance.

Test Case Optimization and Redundancy Reduction Using GA and Neural Networks Itti Hooda; R.S. Chhillar
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 6: December 2018
Publisher : Institute of Advanced Engineering and Science

More than 50% of software development effort is spent in testing phase in a typical software development project. Test case design as well as execution consume a lot of time. Hence, automated generation of test cases is highly required. Here a novel testing methodology is being presented to test object-oriented software based on UML state chart diagrams. In this approach, function minimization technique is being applied and generate test cases automatically from UML state chart diagrams. Software testing forms an integral part of the software development life cycle. Since the objective of testing is to ensure the conformity of an application to its specification, a test “oracle” is needed to determine whether a given test case exposes a fault or not. An automated oracle to support the activities of human testers can reduce the actual cost of the testing process and the related maintenance costs. In this paper, a new concept is being presented using an UML state chart diagram and tables for the test case generation, artificial neural network as an optimization tool for reducing the redundancy in the test case generated using the genetic algorithm. A neural network is trained by the back-propagation algorithm on a set of test cases applied to the original version of the system.

Improving IF Algorithm for Data Aggregation Techniques in Wireless Sensor Networks Madhav Ingle; PVRD Prasada Rao
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 6: December 2018
Publisher : Institute of Advanced Engineering and Science

In Wireless Sensor Network (WSN), fact from different sensor nodes is collected at assembling node, which is typically complete via modest procedures such as averaging as inadequate computational power and energy resources. Though such collections is identified to be extremely susceptible to node compromising attacks. These approaches are extremely prone to attacks as WSN are typically lacking interfere resilient hardware. Thus, purpose of veracity of facts and prestige of sensor nodes is critical for wireless sensor networks. Therefore, imminent gatherer nodes will be proficient of accomplishment additional cultivated data aggregation algorithms, so creating WSN little unresisting, as the performance of actual low power processors affectedly increases. Iterative filtering algorithms embrace inordinate capacity for such a resolution. The way of allocated the matching mass elements to information delivered by each source, such iterative algorithms concurrently assemble facts from several roots and deliver entrust valuation of these roots. Though suggestively extra substantial against collusion attacks beside the modest averaging techniques, are quiet vulnerable to a different cultivated attack familiarize. The existing literature is surveyed in this paper to have a study of iterative filtering techniques and a detailed comparison is provided. At the end of this paper new technique of improved iterative filtering is proposed with the help of literature survey and drawbacks found in the literature.

Hilbert Based Testing of ADC Differential Non-linearity Using Wavelet Transform Algorithms Emad A. Awada
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 6: December 2018
Publisher : Institute of Advanced Engineering and Science

In testing Mixed Signal Devices such as Analog to Digital and Digital to Analog Converters, some dynamic parameters, such as Differential Non-Linearity and Integral Non-linearity, are very critical to evaluating devises performance. However, such analysis has been notorious for complexity and massive compiling process. Therefore, this research will focus on testing dynamic parameters such as Differential Non-Linearity by simulating numerous numbers of bits Analog to Digital Converters and test the output signals base on new testing algorithms of Wavelet transform based on Hilbert process. Such a new testing algorithm should enhance the testing process by using less compiling data samples and prompt testing results. In addition, new testing results will be compared with the conventional testing process of Histogram algorithms for accuracy and enactment.

A Context-based Numeral Reading Technique for Text to Speech Systems Soumya Priyadarsini Panda; Ajit Kumar Nayak
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 6: December 2018
Publisher : Institute of Advanced Engineering and Science

This paper presents a novel technique for context based numeral reading in Indian language text to speech systems. The model uses a set of rules to determine the context of the numeral pronunciation and is being integrated with the waveform concatenation technique to produce speech out of the input text in Indian languages. For this purpose, the three Indian languages Odia, Hindi and Bengali are considered. To analyze the performance of the proposed technique, a set of experiments are performed considering different context of numeral pronunciations and the results are compared with existing syllable-based technique. The results obtained from different experiments shows the effectiveness of the proposed technique in producing intelligible speech out of the entered text utterances compared to the existing technique even with very less storage and execution time.

Generating Non-redundant Multilevel Association Rules Using Min-max Exact Rules R. Vijaya Prakash; S. S. V. N. Sarma; M. Sheshikala
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 6: December 2018
Publisher : Institute of Advanced Engineering and Science

Association Rule mining plays an important role in the discovery of knowledge and information. Association Rule mining discovers huge number of rules for any dataset for different support and confidence values, among this many of them are redundant, especially in the case of multi-level datasets. Mining non-redundant Association Rules in multi-level dataset is a big concern in field of Data mining. In this paper, we present a definition for redundancy and a concise representation called Reliable Exact basis for representing non-redundant Association Rules from multi-level datasets. The given non-redundant Association Rules are loss less representation for any datasets.

Credit Scoring Using Classification and Regression Tree (CART) Algorithm and Binary Particle Swarm Optimization Reza Firsandaya Malik; Hermawan Hermawan
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 6: December 2018
Publisher : Institute of Advanced Engineering and Science

Credit scoring is a procedure that exists in every financial institution. A way to predict whether the debtor was qualified to be given the loan or not and has been a major concern in the overall steps of the loan process. Almost all banks and other financial institutions have their own credit scoring methods. Nowadays, data mining approach has been accepted to be one of the well-known methods. Certainly, accuracy was also a major issue in this approach. This research proposed a hybrid method using CART algorithm and Binary Particle Swarm Optimization. Performance indicators that are used in this research are classification accuracy, error rate, sensitivity, specificity, and precision. Experimental results based on the public dataset showed that the proposed method accuracy is 78 %. In compare to several popular algorithms, such as neural network, logistic regression and support vector machine, the proposed method showed an outstanding performance.

High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit Agung Setiabudi; Hiroki Tamura; Koichi Tanno
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 6: December 2018
Publisher : Institute of Advanced Engineering and Science

A new high speed, low pedestal error bootstrapped CMOS sample and hold (S/H) circuit is proposed for high speed analog-to-digital converter (ADC). The proposed circuit is made up of CMOS transmission gate (TG) switch and two new bootstrap circuits for each transistor in TG switch. Both TG switch and bootstrap circuits are used to decrease channel charge injection and on-resistance input signal dependency. In result, distortion can be reduced. The decrease of channel charge injection input signal dependency also makes the minimizing of pedestal error by adjusting the width of NMOS and PMOS of TG switch possible. The performance of the proposed circuit was evaluated using HSPICE 0.18-m CMOS process. For 50 MHz sinusoidal 1 V peak-to-peak differential input signal with a 1 GHz sampling clock, the proposed circuit achieves 2.75 mV maximum pedestal error, 0.542 mW power consumption, 90.87 dB SNR, 73.50 SINAD which is equal to 11.92 bits ENOB, -73.58 dB THD, and 73.95 dB SFDR.

Strategy for Foreground Movement Identification Adaptive to Background Variations K. Anuradha; N.R. Raajan
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 6: December 2018
Publisher : Institute of Advanced Engineering and Science

Video processing has gained a lot of significance because of its applications in various areas of research. This includes monitoring movements in public places for surveillance. Video sequences from various standard datasets such as I2R, CAVIAR and UCSD are often referred for video processing applications and research. Identification of actors as well as the movements in video sequences should be accomplished with the static and dynamic background. The significance of research in video processing lies in identifying the foreground movement of actors and objects in video sequences. Foreground identification can be done with a static or dynamic background. This type of identification becomes complex while detecting the movements in video sequences with a dynamic background. For identification of foreground movement in video sequences with dynamic background, two algorithms are proposed in this article. The algorithms are termed as Frame Difference between Neighboring Frames using Hue, Saturation and Value (FDNF-HSV) and Frame Difference between Neighboring Frames using Greyscale (FDNF-G). With regard to F-measure, recall and precision, the proposed algorithms are evaluated with state-of-art techniques. Results of evaluation show that, the proposed algorithms have shown enhanced performance.

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Tole Sutikno

Contact Email
ijece@iaesjournal.com

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ijece@iaesjournal.com

Editorial Address
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Location
Kota yogyakarta,

Daerah istimewa yogyakarta

INDONESIA

Abstract

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Home Page

OAI Link

Editorial Team

Contact

Reviewer

Google Scholar

Contact Name Tole Sutikno

Contact Email ijece@iaesjournal.com

Phone -

Journal Mail Official ijece@iaesjournal.com

Editorial Address -

Location Kota yogyakarta, Daerah istimewa yogyakarta INDONESIA

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Contact Name
Tole Sutikno

Contact Email
ijece@iaesjournal.com

Phone
-

Journal Mail Official
ijece@iaesjournal.com

Editorial Address
-

Location
Kota yogyakarta,

Daerah istimewa yogyakarta

INDONESIA