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International Journal of Reconfigurable and Embedded Systems (IJRES)

IJRES
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Published by Institute of Advanced Engineering and Science

ISSN : 20894864 EISSN : 27222608 DOI : -

Core Subject : Economy,

Economics, Econometrics & Finance

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.

Arjuna Subject : -

Articles 5 Documents

Search results for , issue "Vol 1, No 1: March 2012" : 5 Documents clear

Real-time Optical-flow Computation for Motion Estimation under Varying Illumination Conditions Julio C. Sosa; Roberto Rodríguez; Víctor H. García Ortega; Rubén Hernández
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 1: March 2012
Publisher : Institute of Advanced Engineering and Science

The optical flow approach has emerged as a major technique for estimating object motion in image sequences. However, the obtained results by most optical flow techniques are poor because they are strongly affected by large illumination changes and by motion discontinuities. On the other hand, there have been two thrusts in the development of optical flow algorithms. One has emphasized higher accuracy; the other faster implementation. These two thrusts have been independently pursed, without addressing the accuracy vs. efficiency trade-offs. The optical flow computation requires high computing resources and is highly affected by changes in the illumination conditions in most of the existing techniques. In this paper, a new strategy for image sequence processing is proposed. The data reduction achieved with this strategy allows a faster optical flow computation. In addition, the proposed architecture is a hardware custom implementation in EP1S60F1020 FPGA showing the achieved performance.

Simplified VHDL Coding of Modified Non-Restoring Square Root Calculator Tole Sutikno; Aiman Zakwan Jidin; Auzani Jidin; Nik Rumzi Nik Idris
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 1: March 2012
Publisher : Institute of Advanced Engineering and Science

Square root calculation is one of the most useful and vital operation in digital signal processing which in recent generations of processors, the operation is performed by the hardware. The hardware implementation of the square root operation can be achieved by different means, but it is very dependent on programmer's sense and ability to write efficient hardware designs. This paper offers universal and shortest VHDL coding of modified non-restoring square root calculator. The main principle of the method is similar with conventional non-restoring algorithm, but it only uses subtract operation and append 01, while add operation and append 11 is not used. The strategy has conducted to implement successfully in FPGA hardware, and offer an efficient in hardware resource, and it is superior.

A Novel High Speed FPGA Architecture for FIR Filter Design Sachin B. Jadhav; Nikhil Niwas Mane
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 1: March 2012
Publisher : Institute of Advanced Engineering and Science

This paper presents the details of hardware implementation of linear phase FIR filter using merged MAC architecture. Speed of convolution operation of FIR filter is improved using merged MAC architecture. By exploiting the reduced complexity made possible by the use of sparse powers of two partial products terms coefficients, an FIR filter tap can be implemented with 2B full adders, and 2B latches, where B is intermediate wordlegnth. Word and bit level parallelism allows high sampling rates, limited only by the full adder delay. The proposed architecture is based on binary tree constructed using modified 4:2 and 5:2 compressor circuits. Increasing the speed of operation is achieved by using higher modified compressors in critical path. Our objective of work is, to increase the speed of multiplication and accumulation operation by minimizing the number of combinational gates using higher n: 2 compressors, which is required more for Array multiplier at the time of implementation of array architecture. This novel architecture allows the implementation of high sampling rate filters of significant length on FPGA Spartan-3 device (XC3S400 PQ-208). The simulation result shows convolution output of digital FIR filter which is done using Questa Sim 6.4c Mentor Graphics tool. The experimental test of the proposed digital FIR filter is done using Spartan-3 device (XC3S400 PQ-208)

Effectual SVPWM Techniques and Implementation of FPGA Based Induction Motor Drive Saravanan M; Nandakumar R; Veerabalaji G
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 1: March 2012
Publisher : Institute of Advanced Engineering and Science

This paper presents a field programmable gate array(FPGA)-based control integrated circuits(IC) for controlling the pulsewidth modulation (PWM) inverter used in power conditioning system for ac-voltage regulation. Space vector pulsewidth modulation(SVPWM) algorithm offers great flexibility to optimise switching waveform. Among them,double edge triggering can be implemented, It consumes less power compare to other PWM techniques. The SVPWM pulses thus generated through Xilinx is given as switching pulses to voltage source inverter(VSI) circuit to trigger the motor. The delay time of PWM output is programmable and SVPWM control IC is reprogrammable.It shows the advantage of lower total harmonic distortion(THD) without increasing the switching losses. Results are provided along with simulation analysis in terms of THD,output fundamental voltage and voltage transfer ratio to verify the feasibility of operation. The SVPWM switching pattern has been achieved with a fundamental frequency of 50HZ.

A Novel FPGA based Leading One Anticipation Algorithm for Floating Point Arithmetic Units Ashwini Suresh Deshmukh
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 1: March 2012
Publisher : Institute of Advanced Engineering and Science

In multimedia Systems-on-Chips, the design of specialized IEEE-754-compliant floating point arithmetic units (FPU) is critical with respect to both operating speed and silicon area demand. Leading one anticipation is a well-known issue in the implementation of high speed FPUs. We investigated a novel leading one anticipation algorithm allowing us to significantly reduce the anticipation failure rate with respect to the state-of the art. We embedded our technique into a complete FPU and compared its performance against existing solutions, definitely showing both area savings and total latency reduction.

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Journal Mail Official
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Location
Kota yogyakarta,

Daerah istimewa yogyakarta

INDONESIA