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INDONESIA
Indonesian Journal of Electrical Engineering and Computer Science
Published by Institute of Advanced Engineering and Science
ISSN : 25024752     EISSN : 25024760     DOI : -
Core Subject :
Arjuna Subject : -
Articles 63 Documents
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Search results for , issue "Vol 14, No 2: May 2019" : 63 Documents clear
Study of single layer microwave absorber based on rice husk Ash/CNTs composites Y.S. Lee; F.H. Wee; K.Y. You; Z. Liyana; C.Y Lee; Mas Elyna Azol; M.H. Ramli; H.S. Gan; M.S. Shakhirul; Nurulbariah Idris; E.M. Cheng
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp929-936

Abstract

This paper presents the study of microwave absorption single layer microwave absorber based on rice husk ash (RHA) with additional carbon nanotubes (CNTs) filler loading into the composites. The relative permittivity of RHA and CNTs composites (RHA/CNTs) were measured by using Agilent high temperature probe and 85070E software. The CST-MWS software is used to design and evaluate the microwave absorption of RHA and RHA/CNTs with metal backed plate. The microwave absorption of simulated and measured results is compared. The RHA microwave absorber only absorbed maximum, -8 dB at 10.8 GHz of the incident electromagnetic radiation and the RHA/CNTs absorbed less than -15 dB with wider bandwidth over 10.8 GHz to 12.8 GHz compare with RHA composites single layer microwave absorber. The results indicated that the RHA/CNTs composites have enhanced the microwave absorption of RHA composites.
Energy efficient clustereing method for wireless sensor network Chaitra HV; Dr. Ravikumar G.K
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp1039-1048

Abstract

Wireless sensor has attained wide interest across various industries due to availability of low cost sensor device. Preserving battery/energy of these sensor device is most desired. Recently, many approaches has been presented to improve lifetime of sensor network adopting clustering technique. Cluster head selection play an important factor in improving lifetime of cluster based network. For improving cluster head selection multi-objective function are presented in recent time by adopting evolutionary computing and metaheuristic algorithm. However, the existing model incurs computation overhead due to NP-Hard problem and connectivity issues is not considered. Thus affecting network performance. To address the research issues, this work present a novel Multi-objective imperialist competitive algorithm (MOICA) for cluster head selection and routing optimization. Experiment are conducted to evaluate the performance of MOICA over LEACH in term of lifetime performance considering first sensor node death and 75% sensor node death. The outcome shows MOICA achieves significance improvement over LEACH based protocols. 
An overview of available metamaterial-based antenna for non-invasive hyperthermia cancer treatment Nabilah Abdul Jaffar; Norlida Buniyamin; Kasumawati Lias
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp697-705

Abstract

This paper presents the outcome of a literature review that an overview of various types of antenna and metamaterial applicator performance towards cancerous tissue or cell for non-invasive hyperthermia cancer treatment (NIHCT) procedure. From the review, it shows that when LHM lens integrated with an antenna, focusing capabilities of the antenna towards the cancerous area can be improved. However, current applicators have a poor focusing effect when directed towards the actual tumor area. In conjunction with that, this paper proposes a new design of modified applicator that is microstrip antenna integrated with left-handed metamaterial (LHM) lens. The antenna termed microstrip-LHM (M-LHM) lens antenna is proposed for use in NIHCT. It is expected to improve the focusing capabilities of an antenna which is used to kill the cancerous area and thus improve the hyperthermia cancer treatment procedure success rate. In addition, this paper provides an overview of heating techniques used in hyperthermia to enhance focusing capabilities and a few metamaterial advantages that can improve the focusing effect and reduced the hot-spots. Specific Absorption Rate (SAR) will be investigated to evaluate the focusing abilities of the proposed applicator using the SEMCAD X Solver.
Computer aided system for lymphoblast classification to detect acute lymphoblastic leukemia Syadia Nabilah Mohd Safuan; Mohd Razali Md Tomari; Wan Nurshazwani Wan Zakaria; Mohd Norzali Haji Mohd; Nor Surayahani Suriani
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp597-607

Abstract

Acute lymphoblastic leukemia (ALL) is a disease that is detected by the presence of lymphoblast cell. Basically, lymphoblast cell is the abnormal cell of lymphocyte which is one of the White Blood Cell (WBC) types. Early prevention is suggested as this disease can be fatal and caused death. Traditionally, ALL is detected by using manual analysis which is challenging and time consuming. It can also yield inaccurate result as it is highly dependent on the pathologist’s skills. Industry has come out with hematology counter which is fast, accurate and automated. However, these machines are costly and cannot be afforded by some countries. For that reason, Computer Aided System (CAS) will be a great help to the pathologist for assisting purposes and it also can act as second opinion for the pathologist. This system contains six main steps which are color space correction, WBC segmentation, post processing, clumped area extraction, feature extraction and lymphoblast classification. Firstly, color space correction is apply by using l*a*b* color space to standardize the image’s intensity. Next, WBC segmentation is made to prune out WBC region using color space analysis with Otsu thresholding. However, segmented image contains noises that need to be eliminated and it is accomplished by applying morphological filter with Connected Component Labelling (CCL). There is an overlapping WBC which need to be separated by using Watershed method to extract the individual cells. Next, feature extraction is made to collect the cell’s data to be fed into the classifier. Classifier used in this system to classify lymphoblast is Support Vector Machine (SVM) and this system is able to achieve 96.69% of accuracy.
Enhancement of optical code division multiple access system based on 2D ZCC/MD spectral/spatial code Rima Matem; S. A. Aljunid; M. N Junita; C. B. M Rashidi; Israa Shihab Aqrab
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp661-667

Abstract

The combination of 1D zero cross correlation (ZCC) and 1D Multi Diagonal (MD) results a new two dimensional hybrid called 2D ZCC/MD code for spectral/spatial OCDMA system. The proposed code aims to enhance the functional qualities of Optical Code Division Multiple Access (OCDMA) and to overcome the limitations of one dimensional codes. In this paper,   2D ZCC/MD is evaluated at data rate; 622Mbps.  A comparison of the proposed 2D ZCC/MD code to 1D Random Diagonal (RD) and 1D Modified Double Weight (MDW) highlight that 2D ZCC/MD  can support  a large number of active  users even at the higher user bit rate. Furthermore, in term of effective power 2D ZCC/MD can achieve lower effective power.
Design and implementation of embedded concurrent laser missile jammer system using FPGA Chin Beng. Lim; Muataz H. Salih
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp780-787

Abstract

In real time system, every second takes into count as any extra delay could cause critical consequences. Nowadays, almost every system involving multiple data processing. To handle multiple data at the same time, spatial parallelism is required to enhance system performance and provide multitasking feature. Currently, frequency jamming system only can jam one signal at a time. When it comes to missile jamming, the delaying in processing the frequency could cause serious impact as there will be multiple missiles launched to hit a target. These missiles just need few seconds to hit the target within range. Laser missile jammer is designed, which can jam multiple missiles at a time from different directions. The potentials of Field Programmable Gate Array (FPGA) and spatial parallelism is used in this system, to enhance the performance of the system by increasing operating frequency, system throughput, decreasing system cost, power consumption of the system, and get lower complexity. Quartus II version 14.1 is used in this project as a development CAD tool, the entire system implemented on FPGA DE1-SoC board. Also, other components such as Laser Detector, Laser Transmitter, and monitoring screen is integrated with the board. A signal emulator module was designed, to generate signals for on-board self-testing purpose, this system can detect the frequency of laser missile and create an over-powered signal with similar frequency to jam the missile(s) through diffused plates. All the results are shown on control display. This system had achieved a better throughput and lower complexity in terms of less resource usage (3153 Logic Elements) and high operating frequency (up to 1.6 GHz).
Gateway sink placement for sensor node grid distribution in lora smart city networks Nur Aishah Bt. Zainal; Mohamed Hadi Habaebi; Israth Jahan Chowdhury; Md Rafiqul Islam; Jamal I. Daoud
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp834-842

Abstract

Low Power Wide Area Network (LPWAN) is a type of wireless communication network designed to allow long range communications at a low bit rate among things (connected objects), such as sensors operated on a battery. It is a new technology that operates in unauthorized spectrum which designed for wireless data communication [1]. It is used in Internet of Thing (IoT) applications and M2M communications. It provides multi-year battery lifetime and is intended for sensors and applications that need to transmit only a few information over long distances a few times per hour from different environments. In order to have an insight of such long range technology, this paper evaluates the performance of LoRa radio links under shadowing effect and realistic smart city utilities node grid distribution. Such environment is synonymous to residential, industrial and modern urban centers. The focus is to include the effect of shadowing on the radio links while attempting to study the optimum sink node numbers and their locations for maximum sensor node connectivity. Results indicate that the usual unrealistic random node distribution does not reflect actual real-life scenario where many of the these sensing nodes follow the utilities infrastructure around the city (e.g., street light posts, water and gas delivery pipes,…etc). The system is evaluated in terms of connectivity and packet loss ratio.
Design of low power 8-bit gate-diffusion input (GDI) full adder using variable body bias (VBB) technique in 90nm technology Woo Wei Kai; Nabihah Ahmad; Mohamad Hairol Jabbar
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp912-920

Abstract

In digital system, the full adders are fundamental circuits that are used for arithmetic operations. Adder operation can be used to implement and perform calculation of the multipliers, subtraction, comparators, and address operation in an Arithmetic Logic Unit (ALU). The subthreshold leakage current increasing as proportional with the scaling down of oxide thickness and transistor in short channel sizes. In this paper, a Gate-diffusion Input (GDI) circuit design technique allow minimization the number of transistor while maintaining low complexity of logic design and low power realization of Variable Body Biasing (VBB) technique to reduce the static power consumption. The Silterra 90nm process design kit (PDK) was used to design 8-bit full adder with VBB technique in full custom methodology by using Synopsys Electronic Design Automation (EDA) tools. The simulation of 8-bit full adder was compared within a conventional bias technique and VBB technique with operating voltage of  supply. The result showed the reduction of VBB technique in term of peak power,  and average power,   compare with conventional bias technique. Moreover, the Power Delay Product (PDP) showed 1.29pJ in VBB technique compare with conventional bias mode 1.67pJ. The area size of 8-Bit full adder was 10μm×23μm.
Manual clock distribution technique in partitioning stage for multi-FPGA prototyping Salahuddin Savugathali; Muslim Mustapa; Fazrul Faiz Zakaria
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp637-645

Abstract

As the complexity of ASIC/SoC design is increasing along with the number of logic gates, a prototyping process in the verification stage is facing a challenge when the ASIC/SoC design cannot fit into a single FPGA. A solution to prototyping multi-million logic gates of ASIC/SoC circuit into the FPGA platform for verification purpose is by partition the design into multi-FPGA. There are various implementation tools and platform available in the market which automates an FPGA-based prototype phase such as Cadence Protium Rapid Prototyping Platform, Synopsys and S2C. In this paper, Synopsys protocompiler tool will be used to perform the prototyping process of the large 4 core CPU based circuit into the HAPS-80 FPGA platform. This paper will be focusing on the partition requirement needed to successfully prototype the large SoC circuit into the multi-FPGA. The presence of cut clocks in a circuit after partition stage will resulting to the failure in routing stage due to the congestion error. In this paper, two techniques are used, which is automatic clock replication by the Synopsys Protocompiler tool and our proposed technique which is Manual Clock Distribution technique to solve the presence of the cut clock, so that the circuit is able to meet the partition requirement to complete the prototyping process into multi-FPGA. Obtained result from the proposed technique showing that prototyping the large SoC circuit into the multi-FPGA platform has met the specification by eliminating 100% presence of cut clock.
A memristor-based chaotic-masking for analog spread-spectrum communication Muhammad Taher Abuelma’atti; Abdullah Yousef Alnafisa
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp966-971

Abstract

This paper presents a simple chaotic-masking system. The system uses a chaos generator built around a grounded memristor. The memristor is emulated using the current-feedback operational amplifier (CFOA). At the sending end the signal is masked by adding chaos. At the receiving end the signal is recovered by subtracting the chaos. The performance of proposed system is investigated using sinusoidal and square wave signals.

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