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INDONESIA
Indonesian Journal of Electrical Engineering and Informatics (IJEEI)
Published by IAES Indonesia Section and Partners
ISSN : 20893272     EISSN : -     DOI : -
Core Subject : Science, Engineering,
Computer Science & IT Electrical & Electronics Engineering
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) is a peer reviewed International Journal in English published four issues per year (March, June, September and December). The aim of Indonesian Journal of Electrical Engineering and Informatics (IJEEI) is to publish high-quality articles dedicated to all aspects of the latest outstanding developments in the field of electrical engineering. Its scope encompasses the engineering of Telecommunication and Information Technology, Applied Computing & Computer, Instrumentation & Control, Electrical (Power), Electronics, and Informatics.
Arjuna Subject : -
Articles 22 Documents
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Search results for , issue "Vol 12, No 3: September 2024" : 22 Documents clear
Design of Robust Centralized PID Optimized LQR Controller for Temperature Control in Single-Stage Refrigeration System Ekengwu, Bonaventure Onyeka; Eze, Paulinus Chinaenye; Muoghalu, Chidiebere Nnaedozie; Asiegbu, Christopher Nnaemeka; Achebe, Patience Nkiruka
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 12, No 3: September 2024
Publisher : IAES Indonesian Section

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.52549/ijeei.v12i3.5629

Abstract

Refrigeration systems are used for many purposes such as food preservation, cooling and others. They require controller to ensure that the refrigerating cycle can go ON and OFF to maintain a setpoint temperature. For instance, in preservation of food or other perishables, deterioration can occur without efficient system to ensure that temperature within refrigerating space is kept at a setpoint value. This paper presents robust centralized proportional integral and derivative (PID) optimized linear quadratic regulator (LQR) temperature control system for single-stage refrigeration system. A composite technique in which PID algorithm was used to adjust the gains of LQR is proposed. The model of single-stage vapour compressor refrigeration (VCR) system was established in terms of the evaporator, compressor, condenser and the expansion valve’s temperatures. An LQR was initially designed. Then a PID optimized LQR was design. The results indicated that the PID optimized LQR controller outperformed the LQR by providing 73.4% and 62.7% improvement for the evaporating temperature, 45.6% and 71.4% improvement for the compression temperature, 30% and 84.6% improvement for the condensing temperature, and lastly 72% and 70.2% improvement for the expansion temperature in terms of response time and settling time. Simulation with test data proved its robustness and effectiveness in tracking setpoint temperature. Generally, the proposed system has shown capacity to offer robust and centralized tracking in the presence of changing setpoint values.  
Comparative Analysis of Hardware Performance for Linear Detection in a Massive MIMO System on FPGA Using the Vivado HLS Tool Ismail, Nurulhuda; Jabbar, Mohamad Hairol; Joret, Ariffuddin; Katiran, Norshidah; Saadon, Eddy Irwan Shah
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 12, No 3: September 2024
Publisher : IAES Indonesian Section

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.52549/ijeei.v12i3.5356

Abstract

This paper compares the performance of hardware implementation for linear detection in a massive MIMO system. The study focuses on Gram matrix inversion solved using two approaches: direct and indirect matrix inversion. Direct matrix inversion is represented by Cholesky Decomposition, while indirect matrix inversion is represented by the Neumann series and the Gauss-Seidel method. The algorithm for inversions, embedded in a C-based function, is virtually implemented on the FPGA using the Vivado HLS tool. The synthesis report categorizes the performance from the FPGA implementation into three parts: timing (ns), cycle latency, and resource utilization. With the same targeted time limit, indirect matrix inversion such as the Neumann series seems to be the fastest algorithm compared to the direct method due to the matrix-matrix multiplication approach. In terms of latency, NS requires more clock cycles to obtain the output compared to others.  Based on the results, the direct inversion method exhibits higher complexity, particularly in timing for clock frequency and resource utilization needed to complete the inversion

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