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All Journal IAES International Journal of Robotics and Automation (IJRA)
Vladimir Hahanov
Kharkov National University of Radio Electronics
Automotive Engineering Electrical & Electronics Engineering

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Vector-logic models of digital circuits for simulation and rendering Vladimir Hahanov; Svetlana Chumachenko; Eugenia Litvinova; Andrii Voronov; Oleh Demchenko; Nataliya Maksymova
IAES International Journal of Robotics and Automation (IJRA) Vol 15, No 2: June 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijra.v15i2.pp319-330

Abstract

Vector-logical in-memory computing for solving modelling for simulation (MOSI) problems by using read-write transactions free of processor instructions is proposed. A parser mechanism has been developed for converting the HDL code of the logical circuit into the internal vector-logical data structures of the MOSI service, addresses of logical vectors of elements. Deductive vectors are generated from the vector-logic model of the digital circuit for fault as address simulation of the input test sets. A mechanism for modelling a fault simulation matrix as the addresses of the deductive vector bits of each element on the test set has been created. The results of good-value and fault as address simulation are rendered and synchronized in the good-value simulation, fault as address simulation, fault simulation matrices on the input set, and on the lines of the logical circuit displayed on the monitor. Modeling and simulation mechanisms encoded and verified using examples of logical circuits of the ISCAS library. The scientific novelty is represented by vector-logical models of digital circuit elements, good-value simulation of test set as address and fault as address simulation of a digital circuit, and fault as address simulation of the input set, using a quadratic simulation matrix.
Vector logic for robotic system on chip design and test Vladimir Hahanov; Svetlana Chumachenko; Eugenia Litvinova; Andrii Voronov; Oleh Demchenko; Nataliya Maksymova
IAES International Journal of Robotics and Automation (IJRA) Vol 15, No 2: June 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijra.v15i2.pp415-426

Abstract

Artificial Intelligence and vector logic of computing do not contradict but cooperate and enrich each other. Logic is the law of existence and development of emerging computing. Logic is functions and structures, models and algorithms, phenomena and processes. Any computing, including artificial intelligence, is logic and nothing else. Emerging computing devices today have hundreds of systems on a chip and memory blocks, which are interconnected by thousands of connecting wires. This encompasses all the logic, functionalities, and structures, which are subject to testing by system methods. To achieve this, a logic vector serves as a generic form for describing functions, structures, and buses in modeling for the simulation of test sets and logic faults as address. Chip-let Interconnect bus is also a logical functionality or structure. They must be tested to diagnose defects by system logic mechanisms. The latter involves modeling to automatically obtain data structures, followed by good-value simulation and simulation of all fault combinations, such as addresses, on the buses segment. For this purpose, vector logic is used to describe functionalities and structures, models and algorithms, faults and tests. Mechanisms and application that assume a harmonious relationship between the model and the algorithm for their processing are considered.
Co-Authors Andrii Voronov Eugenia Litvinova Nataliya Maksymova Oleh Demchenko Svetlana Chumachenko