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All Journal IAES International Journal of Robotics and Automation (IJRA) International Journal of Reconfigurable and Embedded Systems (IJRES)
Amina Guidoum
High Normal School of Kouba
Automotive Engineering Economics, Econometrics & Finance Electrical & Electronics Engineering

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Optimized mapping in 2D and 3D network on chip using Bat algorithm Maamar Bougherara; Rafik Amara; Amina Guidoum
IAES International Journal of Robotics and Automation (IJRA) Vol 15, No 2: June 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijra.v15i2.pp488-502

Abstract

Communication within system-on-chip (SoC) architectures has evolved significantly to keep pace with the growing complexity of modern applications. To overcome the limitations of traditional interconnects, network-on-chip (NoC) has emerged as a scalable and efficient communication solution. Although early NoC designs relied heavily on 2D architectures, their physical and performance constraints have led to the rise of 3D NoC architectures, which offer better spatial integration and improved performance. In order to automate the NoC design process, a number of electronic design automation (EDA) tools and optimization algorithms are employed to help designers achieve efficient and high-performance designs. Within this EDA framework, one of the most critical stages is the core placement or application mapping phase, where computational tasks are allocated to the processing elements of the architecture. This step is very hard due to its combinatorial nature, and its optimization is essential since it directly impacts communication cost, energy consumption, and overall system performance. To address this challenge, numerous heuristic and metaheuristic algorithms have been explored for both 2D and 3D NoCs. In this paper, we propose an adaptation of the bat algorithm to solve the mapping problem in both 2D and 3D NoC architectures, with the objective of minimizing communication cost. The proposed approach is evaluated and compared against other optimization methods to assess its effectiveness in enhancing NoC performance within the EDA framework.
Crow search algorithm for efficient IP placement in 2D and 3D network-on-chip architectures Maamar Bougherara; Amina Guidoum; Rafik Amara
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 2: July 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i2.pp373-385

Abstract

The communication in system-on-chip (SoC) has evolved to meet the increas-ingly complex requirements of modern applications. To address connectivity challenges, the network-on-chip (NoC) has emerged as an efficient solution. While traditional NoCs are primarily based on 2D architectures, the inherent limitations of 2D designs have driven the adoption of 3D architectures, which offer enhanced space utilization and performance optimization. A key step in the design of NoC systems is the placement of cores, also known as the map-ping phase, in which application tasks are assigned to the architecture’s process-ing elements. This phase is considered an nondeterministic polynomial (NP)-complete problem due to its combinatorial complexity. Optimizing this phase is crucial, as it directly impacts the overall performance of the NoC. Various opti-mization algorithms have been employed to maximize the efficiency of 2D and 3D NoCs. In this paper, we adopt the crow search algorithm to find the places both 2D and 3D NoCs with minimal comunication. The goal is to evaluate its performance compared to other optimization algorithms in this crucial step.
Co-Authors Maamar Bougherara Rafik Amara