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All Journal Jurnal Ilmiah Dan Karya Mahasiswa
Vania Rahmawati
Politeknik Elektronika Negeri Surabaya
Humanities Computer Science & IT Decision Sciences, Operations Research & Management Economics, Econometrics & Finance Environmental Science Languange, Linguistic, Communication & Media

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Implementasi Engineering Design Process pada Rancang Bangun Logic Gate Trainer Kit sebagai Media Praktikum Siswa SMK Jurusan Teknik Elektronika Vania Rahmawati; Ully Catur Rosaliana; Yuwono Dhanu Ryndra
Jurnal Ilmiah Dan Karya Mahasiswa Vol. 4 No. 5 (2026): Oktober: JURNAL ILMIAH DAN KARYA MAHASISWA (JIKMA)
Publisher : Institut Teknologi dan Bisnis (ITB) Semarang

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.54066/jikma.v4i5.5053

Abstract

Digital circuit learning in vocational high schools (SMK) specializing in Electronics Engineering faces challenges from abstract binary logic and breadboard assembly problems, including poor pin contacts, loose jumper wires, and broken integrated circuit (IC) legs. These issues cause measurement errors and waste practicum time. This study applies the Engineering Design Process (EDP) to develop a robust, modular, and portable Logic Gate Trainer Kit for independent practice. Seven stages comprise problem formulation, datasheet review, interface design, panel vector modeling using CorelDraw, acrylic panel fabrication through laser cutting, point-to-point wiring, and functional evaluation. The trainer integrates six logic gate groups using standard TTL ICs (7408, 7432, and 7404) and Low-power Schottky variants (74LS00, 74LS86, and 74LS02). An adapter converts AC electricity into regulated 5 V DC, distributed through a barrier terminal block rail. Functional validation uses mechanical toggle switches to supply binary inputs, with LEDs and a piezoelectric buzzer indicating outputs. Results demonstrate that all gates operate according to Boolean truth tables. The trainer effectively addresses manual wiring difficulties, protects IC pins, optimizes learning time, and improves students’ understanding of digital logic in vocational workshops.  
Co-Authors Ully Catur Rosaliana Yuwono Dhanu Ryndra