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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Patil, S. C.
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Economics, Econometrics & Finance

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IMPLEMENTED WITH DUAL MATERIAL GATE SILICON-ON- INSULATOR JUNCTIONLESS CMOS CIRCUITS Wagaj, S. C.; Patil, S. C.
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v9.i2.pp%p

Abstract

In this research paper, we demonstrate the logic performance of n and p channel complementary metal oxide semiconductor (CMOS) circuits implemented with dual material gate silicon on insulator junctionless transistor (DMG SOI JLT). A comparison of circuit performance of the n and p channel dual material gate silicon on insulator transistor and junctionless transistor. The logic performance of a CMOS circuits is evaluated in terms of static power dissipation, output voltage v/s input voltage, propagation delay and noise margin. When metal oxide semiconductor field effect transistor (MOSFET) in saturation region gate capacitance of junctionless transistor reduces compare to with junction transistor. The circuit simulation result CMOS inverter propagation delay of junctionless transistor is reduced by 25% compare with junction transistor. DMG SOI JLT common source amplifier gives amplification of 1.25 times which is higher than DMG SOI transistor. The noise margin of junctionless CMOS inverter is 23% maximum compared to with junction CMOS inverter. NAND gate static power dissipation of DMG SOI JLT is improved by 53%, 46% and 34% compared to DMG SOI Transistor at 20nm, 30nm and 40nm channel length. On current of dual material gate junctionless transistor is increases when channel length increase compare to with junction transistor. Static power dissipation of junctionless transistor inverter is reduced by 3% compared to with junction transistor inverter at channel length 30nm.
Co-Authors Wagaj, S. C.