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Raza Naqvi, Muhammad
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Computer Science & IT Engineering

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Low power network on chip architectures: A survey Raza Naqvi, Muhammad
Computer Science and Information Technologies Vol 2, No 3: November 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/csit.v2i3.p158-168

Abstract

Mostly communication now days is done through system on chip (SoC) models so, network on chip (NoC) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.
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