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Bhairannawar, Satish S.
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An efficient controller-based architecture for AES algorithm using FPGA Nadaf, Reshma; Bhairannawar, Satish S.
Indonesian Journal of Electrical Engineering and Computer Science Vol 35, No 1: July 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v35.i1.pp397-404

Abstract

The importance of crucial current technical advancements, particularly those centered on the cryptography process such as Cryptographic advanced encryption standard (AES) hardware architectures are gaining momentum with respect to improving the speed and area optimizations. In this paper, we have proposed a novel architecture to implement AES on a reconfigurable hardware i.e., field programmable gate arrays (FPGA). The controller in AES algorithm is responsible to generate the signals to perform operations to generate the 128 bits ciphertext. The proposed controller uses multiplexer and synchronous register-based approach to obtain area and speed efficient on the FPGA hardware. The entire architecture of AES with proposed controller is implemented on Virtex 5, Virtex 6, and Virtex 7series using XilinxISE 14.7 and tested for critical path delay, frequency, slices, efficiency and throughput. It is observed that all the parameters are improved compared to existing architectures achieving the throughput of 32.29, 40.01, and 43.01 Gbps respectively. The key benefit of this approach is the high level of parallelism it displays in a quick and efficient manner.
Co-Authors Nadaf, Reshma