Zaidan, Majeed Rashid
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Improving voltage collapse point under transmission line outage by optimal placement and sizing of SVC using genetic algorithm Zaidan, Majeed Rashid; Hasan, Ghanim Thiab; Bajaj, Mohit; Toos, Saber Izadpanah
International Journal of Applied Power Engineering (IJAPE) Vol 13, No 1: March 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijape.v13.i1.pp213-222

Abstract

In many power systems, voltage instability can increase the risk of voltage collapse and, as a result, turn the power system toward a blackout. Therefore, increasing the voltage collapse point is required. A transmission line outage is an emergency condition in power systems that can lead to voltage instability and voltage collapse. Thus, it is expected to employ shunt-connected flexible AC transmission systems (FACTS) such as the static var compensator (SVC) to increase the voltage collapse point when lines outage. This paper presents the genetic algorithm (GA) application to optimal placement and sizing of an SVC for increasing voltage collapse points following lines outage. The continuation power flow (CPF) technique has been used to determine the maximum loading point (MLP) corresponding to the point of voltage collapse. Also, to reduce the number of scenarios when line outages occur, a list in ascending order is established based on the line outage priority (LOP). The IEEE 14-bus test system is chosen to carry out simulations, and an SVC will be installed in the system based on the GA results. Simulation results confirm the effectiveness of an SVC for improving voltage stability as well as increasing voltage profile.
Emergency congestion management of power systems by static synchronous series compensator Zaidan, Majeed Rashid; Toos, Saber Izadpanah
Indonesian Journal of Electrical Engineering and Computer Science Vol 25, No 3: March 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v25.i3.pp1258-1265

Abstract

From a transmission system point of view, any overload on the grid lines during operation in situations such as peak load or emergency conditions include line outage or generator outage, is refers to congestion. Generally, the congestion can be managed by controlling power flow. On the other hand, series compensation has a significant role in control power flow; therefore, series compensation equipment like fixed series capacitor (FSC), thyristor-controlled series capacitor (TCSC), and static synchronous series compensator (SSSC) can be used for congestion management. In this paper, an SSSC is used in a transmission line to manage congestion in emergency conditions, line outage and generator outage. The congestion rent contribution method has been used to determine the location of the SSSC in the IEEE 14-bus test system. This technique finds the transmission line 1-2 (from bus 1 to bus 2) is the best location of the SSSC to reduce congestion. After installing an SSSC in the specified line, simulation results show that the power flow has been controlled, leading to reducing the congestion. In other words, the effectiveness of the SSSC can be seen in reducing the total congestion rent, the total generation cost, and network losses.
Minimizing the switching losses in the SiC MOSFET by using buried oxide Mutlaq, Ali Hlal; Faraj, Sura Hamad; Zaidan, Majeed Rashid; Hasan, Ghanim Thiab; Names, Ahmed Saad
International Journal of Applied Power Engineering (IJAPE) Vol 14, No 3: September 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijape.v14.i3.pp613-619

Abstract

For optimizing the efficiency of the power switching devices, it is important to reduce the switching power losses. One method to minimize the switching power losses is to reduce the gate drain charge (QGD). In this paper, a 1.2 kV SiC MOSFET device with a buried oxide has been proposed to minimize QGD. The proposed design has been conducted by using the TCAD simulation program. The on-resistance (Ron,sp), QGD have been measured and analyzed based on the width and thickness of the buried oxide layer and compared with the measurement of traditional SiC MOSFET. The obtained results indicate that the QGD of 1.2 kV SiC MOSFET with buried oxide with WBO of 0.25 μm and TBO of 0.3 μm was reduced to about 31.3% which mean a minimize of power losses. The comparison results indicate that the proposed device with a buried oxide layer can be effectively used as an optimum solution for minimizing the power switching losses.