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All Journal International Journal of Electrical and Computer Engineering International Journal of Reconfigurable and Embedded Systems (IJRES)
Lakshmaiah, Gangadharaiah Soralamavu
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Computer Science & IT Economics, Econometrics & Finance Electrical & Electronics Engineering

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Hybrid controller design using gain scheduling approach for compressor systems Muddenahalli Narasimhaiah, Divya; Narayanappa, Chikkajala Krishnappa; Lakshmaiah, Gangadharaiah Soralamavu
International Journal of Electrical and Computer Engineering (IJECE) Vol 12, No 3: June 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v12i3.pp3051-3060

Abstract

The automatic control system plays a crucial role in industries for controlling the process operations. The automatic control system provides a safe and proper controlling mechanism to avoid environmental and quality problems. The control system controls pressure flow, mass flow, speed control, and other process metrics and solves robustness and stability issues. In this manuscript, The Hybrid controller approach like proportional integral (PI) and proportional derivative (PD) based fuzzy logic controller (FLC) using with and without gain scheduling approach is modeled for the compressor to improve the robustness and error response control mechanism. The PI/PD-based FLC system includes step input function, the PI/PD controller, FLC with a closed-loop mechanism, and gain scheduler. The error signals and control response outputs are analyzed in detail for PI/PD-based FLC’s and compared with conventional PD/PID controllers. The PD-based FLC with the Gain scheduling approach consumes less overshoot time of 74% than the PD-based FLC without gain scheduling approach. The PD-based FLC with the gain scheduling approach produces less error response in terms of 7.9% in integral time absolute error (ITAE), 7.4% in integral absolute error (IAE), and 16% in integral square error (ISE) than PD based FLC without gain scheduling approach.
Efficient very large-scale integration architecture design of proportionate-type least mean square adaptive filters Lakshmaiah, Gangadharaiah Soralamavu; Narayanappa, Chikkajala Krishnappa; Shrinivasan, Lakshmi; Narasimhaiah, Divya Muddenahalli
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 1: March 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i1.pp69-75

Abstract

The effectiveness of adaptive filters are mainly dependent on the design techniques and the algorithm of adaptation. The most common adaptation technique used is least mean square (LMS) due its computational simplicity. The application depends on the adaptive filter configuration used and are well known for system identification and real time applications. In this work, a modified delayed μ-law proportionate normalized least mean square (DMPNLMS) algorithm has been proposed. It is the improvised version of the µ-law proportionate normalized least mean square (MPNLMS) algorithm. The algorithm is realized using Ladner-Fischer type of parallel prefix logarithmic adder to reduce the silicon area. The simulation and implementation of very large-scale integration (VLSI) architecture are done using MATLAB, Vivado suite and complementary metal–oxide– semiconductor (CMOS) 90 nm technology node using Cadence register transfer level (RTL) Genus Compiler respectively. The DMPNLMS method exhibits a reduction in mean square error, a higher rate of convergence, and more stability. The synthesis results demonstrate that it is area and delay effective, making it practical for applications where a faster operating speed is required.
Efficient power optimized very-large-scale integration architecture of proportionate least mean square adaptive filter Lakshmaiah, Gangadharaiah Soralamavu; Krishnappa, Narayanappa Chikkajala; Ramappa, Poornima Golluchinnappanahalli; Narasimhaiah, Divya Muddenahally; Radder, Umesharaddy; Chandrasekhar, Chakali
International Journal of Electrical and Computer Engineering (IJECE) Vol 15, No 2: April 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v15i2.pp2513-2522

Abstract

The focus on power optimization in embedded systems is especially important for embedded applications since it has brought in many methods and factors that are necessary for developing systems that are both power- and area-efficient. In contrast to the current delayed wavelet μ-law proportionate least mean square (DWMPLMS) and delayed least mean square (DLMS) algorithms, this work offers the development of adaptive filters based on the least mean square (LMS) method, which improves power and timing performance. In order to improve area and time efficiency, the proportionate least mean square (PLMS) algorithm's architecture has been modified to remove delay, add a proportionate gain block, design for a fixed length, include an approximate multiplier block, and swap out standard blocks for floating-point adder and divider blocks. According to a power and temporal comparison with the DWMPLMS and DLMS algorithms, field-programmable gate array (FPGA) synthesis reduces power usage by 95% for a 32-bit filter length in PLMS when compared to the above methods.
Co-Authors Chandrasekhar, Chakali Krishnappa, Narayanappa Chikkajala Muddenahalli Narasimhaiah, Divya Narasimhaiah, Divya Muddenahalli Narasimhaiah, Divya Muddenahally Narayanappa, Chikkajala Krishnappa Radder, Umesharaddy Ramappa, Poornima Golluchinnappanahalli Shrinivasan, Lakshmi