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All Journal International Journal of Power Electronics and Drive Systems (IJPEDS)
Srivastava, Geetika
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Control & Systems Engineering Electrical & Electronics Engineering

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Novel complementary Sziklai pair based high gain low noise small-signal amplifiers Shukla, SachchidaNand; Arshad, Syed Shamroz; Srivastava, Geetika
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 14, No 4: December 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijpeds.v14.i4.pp2283-2292

Abstract

A new paired configuration of opposite polarity BJTs, the “complementary Sziklai pair” is introduced in the series of multi-BJT-based devices like Darlington and Sziklai pair, and its viability is tested in small-signal common emitter (CE) and common collector (CC) amplifier configurations. The Darlington and Sziklai both face the problem of poor frequency response at a higher frequency which is addressed by the proposed configuration. The proposed pair with CE amplifier holds class-A amplification property with a high voltage gain of 200.05, a high current gain of 11.62, wider bandwidth of 1.64 MHz, and a low THD of 1.29E-6%, hence supports the potential of wide applicability in analog communication. Similarly, the proposed pair with CC configuration produces approximately a unit current gain of 0.99 with wider bandwidth of 1.90 MHz and low THD of 1.76E-6%, therefore it can be used as a current buffer in a generalized current follower circuit. Conclusively, the device structure of this new BJT pair may be considered the third consecutive member of the series of Darlington pair and Sziklai pair. The layout of the proposed CE and CC amplifier occupy small areas of 158.30 μm2 (10.23×15.47 μm) and 141.16 μm2 (10.20×13.84 μm) respectively in 180 nm process technology.
Low power CMOS Gm-C based low pass filter for front end neural signal processing Dixit, Ashish; Srivastava, Geetika; Kumar, Anil; Shukla, Sachchida Nand
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 15, No 1: March 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijpeds.v15.i1.pp559-565

Abstract

The sub 100 µV voltage levels and sub 100 Hz frequency range makes the processing of most popular signal electroencephalograph (EEG) for brain functionality analysis, a complex task. The low frequency content of EEG (useful signals below 70 Hz) is commonly used for diagnosis of various brain related disorders making low-pass filter (LPF) a key block in front-end processing as noise reduction and resolution enhancement is crucial for precise recovery of these information. This paper is aimed to design reduced transconductance (Gm) based low power and small area CMOS LPF with cutoff frequency (fc) around 70 Hz. The proposed design is simulated using Cadence virtuoso tool and gives cut-off frequency of 72.958 Hz with low output noise of 3.0609 µV/√Hz and power consumption of 264.060 nW at operating voltage of 0.4 V. The simulation results show linearity of performance over -40 to 100 °C. Layout of circuit takes up area of 86.74×81.21 µm and post layout simulation shows 5% variation in power consumption as compared to pre layout simulations.
Co-Authors Anil Kumar, Anil Arshad, Syed Shamroz Dixit, Ashish Shukla, Sachchida Nand Shukla, SachchidaNand