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All Journal International Journal of Electrical and Computer Engineering International Journal of Reconfigurable and Embedded Systems (IJRES)
Mark McDermott
Electrical and Computer Engineering C0803 ENS 36E University of Texas at Austin Austin, Texas 78712-0214 USA
Computer Science & IT Economics, Econometrics & Finance Electrical & Electronics Engineering

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Cognitive Sensor Platform Mark McDermott
International Journal of Electrical and Computer Engineering (IJECE) Vol 4, No 4: August 2014
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (618.356 KB)

Abstract

This paper describes a platform that is used to build embedded sensor systems for low energy implantable applications. One of the key characteristics of the platform is the ability to reason about the environment and dynamically modify the operational parameters of the system. Additionally the platform provides to ability to compose application specific sensor systems using a novel computational element that directly supports a synchronous-dataflow (SDF) programming paradigm. Cognition in the context of a sensor platform is defined as the “process of knowing, including aspects of awareness, perception, reasoning, and judgment”.DOI:http://dx.doi.org/10.11591/ijece.v4i4.5680
Queued-Stack Dataflow Processing Element for a Cognitive Sensor Platform Mark McDermott
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 3: November 2012
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (362.885 KB) | DOI: 10.11591/ijres.v1.i3.pp75-86

Abstract

This paper describes a Queued-Stack (QS) Dataflow Processing Element (DPE) that is used in a cognitive sensor platform. The queued-stack is used for buffering input data to the DPE and for storage of variables and results. The queuing mechanism and dataflow protocol provides the capability to compose multi-node computational systems where communication between elements is via non-blocking FIFO channels. System composition is achieved using synchronous dataflow tools such as SDF3 or Ptolemy. The dataflow-processing element is implemented using single cycle micro-coded engine where the ratio of datapath transistors to control logic is optimized for programmable energy-performance sensitive applications.
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