Article Per Year (5 Year)
p-Index From 2021 - 2026
0.23
P-Index
This Author published in this journals
All Journal International Journal of Electrical and Computer Engineering
Gajanan Dhole
Gokhale Education Society's R. H. Sapat College of Engineering, Management Studies and Research
Computer Science & IT Electrical & Electronics Engineering

Published : 1 Documents Claim Missing Document
Claim Missing Document
Check
Articles

Found 1 Documents
Search

 1 
Single core configurations of saturated core fault current limiter performance of laboratory test models Vittesh Naphade; Vilas Ghate; Gajanan Dhole
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 6: December 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v11i6.pp4667-4677

Abstract

Economic growth with industrialization and urbanization lead to an extensive increase in power demand. It forced the utilities to add power generating facilities to cause the necessary demand-generation balance. The bulk power generating stations, mostly interconnected, with the penetration of distributed generation result in an enormous rise in the fault level of power networks. It necessitates for electrical utilities to control the fault current so that the existing switchgear can continue its services without up-gradation or replacement for reliable supply. The deployment of fault current limiter (FCL) at the distribution and transmission networks has been under investigation as a potential solution to the problem. A saturated core fault current limiter (SCFCL) technology is a smart, scalable, efficient, reliable, and commercially viable option to manage fault levels in existing and future MV/HV supply systems. This paper presents the comparative performance analysis of two single-core SCFCL topologies impressed with different core saturations. It has demonstrated that the single AC winding configuration needs more bias power for affecting the same current limiting performance with an acceptable steady-state voltage drop contribution. The fault state impedance has a transient nature, and the optimum bias selection is a critical design parameter in realizing the SCFCL applications.
Co-Authors Vilas Ghate Vittesh Naphade