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Medhat Awadalla

Sultan Qaboos University

Author-ID : 2376066

Computer Science & IT Electrical & Electronics Engineering

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Articles

An Efficient Cache Organization for On-Chip Multiprocessor Networks Medhat Awadalla; Ahmed M. Sadek
International Journal of Electrical and Computer Engineering (IJECE) Vol 5, No 3: June 2015
Publisher : Institute of Advanced Engineering and Science

To meet the growing computation-intensive applications and the needs of low-power, high-performance systems, the number of computing resources in single-chip has enormously increased. By adding many computing resources to build a system in System-on-Chip, its interconnection between each other becomes another challenging issue. In most System-on-Chip applications, a shared bus interconnection which needs an arbitration logic to serialize several bus access requests, is adopted to communicate with each integrated processing unit because of its low-cost and simple control characteristics. This paper focuses on the interconnection design issues of area, power and performance of chip multi-processors with shared cache memory. It shows that having shared cache memory contributes to the performance improvement, however, typical interconnection between cores and the shared cache using crossbar occupies most of the chip area, consumes a lot of power and does not scale efficiently with increased number of cores. New interconnection mechanisms are needed to address these issues. This paper proposes an architectural paradigm in an attempt to gain the advantages of having shared cache with the avoidance of penalty imposed by the crossbar interconnect. The proposed architecture achieves smaller area occupation allowing more space to add additional cache memory. It also reduces power consumption compared to the existing crossbar architecture. Furthermore, the paper presents a modified cache coherence algorithm called Tuned-MESI. It is based on the typical MESI cache coherence algorithm however it is tuned and tailored for the suggested architecture. The achieved results of the conducted simulated experiments show that the developed architecture produces less broadcast operations compared to the typical algorithm.

Performance Enhancement of Multicore Architecture Medhat Awadalla; Hanan Konsowa
International Journal of Electrical and Computer Engineering (IJECE) Vol 5, No 4: August 2015
Publisher : Institute of Advanced Engineering and Science

Multicore processors integrate several cores on a single chip. The fixed architecture of multicore platforms often fails to accommodate the inherent diverse requirements of different applications. The permanent need to enhance the performance of multicore architecture motivates the development of a dynamic architecture. To address this issue, this paper presents new algorithms for thread selection in fetch stage. Moreover, this paper presents three new fetch stage policies, EACH_LOOP_FETCH, INC-FETCH, and WZ-FETCH, based on Ordinary Least Square (OLS) regression statistic method. These new fetch policies differ on thread selection time which is represented by instructions’ count and window size. Furthermore, the simulation multicore tool, , is adapted to cope with multicore processor dynamic design by adding a dynamic feature in the policy of thread selection in fetch stage. SPLASH2, parallel scientific workloads, has been used to validate the proposed adaptation for multi2sim. Intensive simulated experiments have been conducted and the obtained results show that remarkable performance enhancements have been achieved in terms of execution time and number of instructions per second produces less broadcast operations compared to the typical algorithm.

Processor Speed Control for Power Reduction of Real-Time Systems Medhat Awadalla
International Journal of Electrical and Computer Engineering (IJECE) Vol 5, No 4: August 2015
Publisher : Institute of Advanced Engineering and Science

Reducing energy consumption is a critical issue in the design of battery-powered real time systems to prolong battery life. With dynamic voltage scaling (DVS) processors, energy consumption can be reduced efficiently by making appropriate decisions on the processor speed/voltage during the scheduling of real time tasks. Scheduling decision is usually based on parameters which are assumed to be crisp. However, in many circumstances the values of these parameters are vague. The vagueness of parameters suggests that to develop a fuzzy logic approach to reduce energy consumption by determining the appropriate supply-voltage/speed of the processor provided that timing constraints are guaranteed. Intensive simulated experiments and qualitative comparisons with the most related literature have been conducted in the context of dependent real-time tasks. Experimental results have shown that the proposed fuzzy scheduler saves more energy and creates feasible schedules for real time tasks. It also considers tasks priorities which cause higher system utilization and lower deadline miss time.

Customized Hardware Crypto Engine for Wireless Sensor Networks Medhat Awadalla; Ahmed Al Maashri; Lavanya Pathuri; Afaq Ahmad
Indonesian Journal of Electrical Engineering and Computer Science Vol 7, No 1: July 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v7.i1.pp263-275

Nowadays, managing for optimal security to wireless sensor networks (WSNs) has emerged as an active research area. The challenging topics in this active research involve various issues such as energy consumption, routing algorithms, selection of sensors location according to a given premise, robustness, and efficiency. Despite the open problems in WSNs, already a high number of applications available shows the activeness of emerging research in this area. Through this paper, authors propose an alternative routing algorithmic approach that accelerate the existing algorithms in sense to develop a power-efficient crypto system to provide the desired level of security on a smaller footprint, while maintaining real-time performance and mapping them to customized hardware. To achieve this goal, the algorithms have been first analyzed and then profiled to recognize their computational structure that is to be mapped into hardware accelerators in platform of reconfigurable computing devices. An intensive set of experiments have been conducted and the obtained results show that the performance of the proposed architecture based on algorithms implementation outperforms the software implementation running on contemporary CPU in terms of the power consumption and throughput.

Co-Authors Afaq Ahmad Ahmed Al Maashri Ahmed M. Sadek Hanan Konsowa Lavanya Pathuri

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