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Gurmohan Singh
Centre for Development of Advanced Computing, Mohali
Computer Science & IT Electrical & Electronics Engineering

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High Performance Low Power Dual Edge Triggered Static D Flip-Flop Gagandeep Singh; Gurmohan Singh; Vemu Sulochna
International Journal of Electrical and Computer Engineering (IJECE) Vol 3, No 5: October 2013
Publisher : Institute of Advanced Engineering and Science

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Abstract

In this paper a low-power double-edge triggered static flip-flop (DETSFF) suitable for low-power and high performance applications is presented. The designed DETFF is verified at gpdk 180nm-1.8V CMOS technology. Comparison with some of the latest DETFFs shows that the proposed DETSFF can achieve the lowest power consumption, lowest clock to Q delay and thus Power-delay-product (PDP). Moreover, the proposed DETSFF comprises of only 15 transistors hence require lesser number of transistors and thus requires lesser overall silicon area.DOI:http://dx.doi.org/10.11591/ijece.v3i5.3164
Co-Authors Gagandeep Singh Vemu Sulochna