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Ahmed M. Hasan
University of Technology
Computer Science & IT Electrical & Electronics Engineering

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Design and implementation of proposed 320 bit RC6-cascaded encryption/decryption cores on altera FPGA Ashwaq T. Hashim; Ahmed M. Hasan; Hayder M. Abbas
International Journal of Electrical and Computer Engineering (IJECE) Vol 10, No 6: December 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v10i6.pp6370-6379

Abstract

This paper attempts to build up a simple, strong and secure cryptographic algorithm. The result of such an attempt is “RC6-Cascade” which is 320-bits RC6 like block cipher. The key can be any length up to 256 bytes. It is a secret-key block cipher with precise characteristics of RC6 algorithm using another overall structure design. In RC6-Cascade, cascading of F-functions will be used instead of rounds. Moreover, the paper investigates a hardware design to efficiently implement the proposed RC6-Cascade block cipher core on field programmable gate array (FPGA). An efficient compact iterative architecture will be designed for the F-function of the above algorithm. The goal is to design a more secure algorithm and present a very fast encryption core for low cost and small size applications.
Co-Authors Ashwaq T. Hashim Hayder M. Abbas