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All Journal International Journal of Electrical and Computer Engineering
Azzad Bader Saeed
University of Technology
Computer Science & IT Electrical & Electronics Engineering

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Signalling load reduction in 5G network based on cloud radio access network architecture Mohammed Abbas Waheed; Azzad Bader Saeed; Thanaa Hussein Abd
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 6: December 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v11i6.pp5127-5136

Abstract

The rapid growth of both mobile users and application numbers has caused a huge load on the core network (CN). This is attributed to the large numbers of control messages circulating between CN entities for each communication or service request, however, making it imperative to develop innovative designs to handle this load. Consequently, a variety of proposed architectures, including a software defined network (SDN) paradigm focused on the separation of control and data plans, have been implemented to make networks more flexible. Cloud radio access network (C-RAN) architecture has been suggested for this purpose, which is based on separating base band units (BBU) from several base stations and assembling these in one place. In this work, a novel approach to realize this process is based on SDN and C-RAN, which also distributes the control elements of the CN and locates them alongside the BBU to obtain the lowest possible load. The performance of this proposed architecture was evaluated against traditional architecture using MATLAB simulation, and. the results of this assessment indicated a major reduction in signalling load as compared to that seen in the traditional architecture. Overall, the number of signalling messages exchanged between control entities was decreased by 53.19 percent as compared to that seen in the existing architecture.
Elevator controller based on implementing a random access memory in FPGA Azzad Bader Saeed
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 2: April 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v11i2.pp1053-1062

Abstract

Previous techniques of elevator controllers suffer from two main challenges: processing time, and software size. In this work these challenges have been overcame by implementing a controller random access memory (RAM) in a fast FPGA for a proto-type of two-floors elevator, as known the RAM and FPGA are fast devices. A look-up-table LUT (which is fast technique) has been proposed for this work, this LUT has represented a proposed relation between 10 and 7 lines, the states of the sensors and switches have been represented by the 10 input lines, and the commands for the motors of slide door and traction machine have been represented by the 7 output lines. The proposed LUT has been schematically realize by a (10×7) bits RAM which has been implemented in field programmable gate arrays (FPGA). The proposed system has been performed using 'ISE Design Suit' software package and FPGA Spartan6 SP-605 evaluation kit, the clock frequency of this FPGA is 200 MHz which is respectively high. The processing time and software size of the proposed controller had reached to 20ns and 3.75 MB, which they are less than that obtained from the results of previous techniques.
Co-Authors Mohammed Abbas Waheed Thanaa Hussein Abd