Article Per Year (5 Year)
p-Index From 2021 - 2026
0.339
P-Index
This Author published in this journals
All Journal International Journal of Electrical and Computer Engineering TELKOMNIKA (Telecommunication Computing Electronics and Control)
Ziyad Khalaf Farej
Northern Technical University
Computer Science & IT Electrical & Electronics Engineering

Published : 2 Documents Claim Missing Document
Claim Missing Document
Check
Articles

Found 2 Documents
Search

 1 
Performance evaluation of the IEEE 802.11n random topology WLAN with QoS application Ziyad Khalaf Farej; Mustafa Mohammad Jasim
International Journal of Electrical and Computer Engineering (IJECE) Vol 10, No 2: April 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (3239.071 KB) | DOI: 10.11591/ijece.v10i2.pp1924-1934

Abstract

The IEEE 802.11n supports high data rate transmissions due its physical layer Multiple Input ‎Multiple Output (MIMO) advanced antenna system and MAC layer enhancement features (frame ‎aggregation and block acknowledgement). As a result this standard is very suitable for multimedia ‎services through its Enhanced Distributed Channel Access (EDCA). This paper focuses on ‎evaluating the Quality of Service (QoS) application on the performance of the IEEE 802.11n ‎random topology WLAN. Three different number of nodes (3, 9 and 18) random topology with one ‎access point are modeled and simulated by using the Riverbed OPNET 17.5 Modular to ‎investigate the Wireless Local Area Network (WLAN) performance for different spatial streams. ‎The result clarified the impact of QoS application and showed that its effect is best at the 18 node ‎number topology. For a 4x4 MIMO, when QoS is applied and with respect to the no QoS ‎application case, simulation results show a maximum improvement of 86.4%, 33.9%, 52.2% and ‎‎68.9% for throughput, delay, data drop and retransmission attempts, respectively. ‎
Simulation-based fault-tolerant multiprocessors system Ahmad F. Al-Allaf; Ziyad Khalaf Farej
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 21, No 2: April 2023
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v21i2.24253

Abstract

System reliability is an important issue in designing modern multiprocessor systems. This paper proposes a fault-tolerant, scalable, multiprocessor system architecture that adopts a pipeline scheme. To verify the performance of the proposed system, the SimEvent/Stateflow tool of the MATLAB program was used to simulate the system. The proposed system uses twelve processors (P), connected in a linear array, to build a ten-stage system with two backup processors (BP). However, the system can be expanded by adding more processors to increase pipeline stages and performance, and more backup processors to increase system reliability. The system can automatically reorganize itself in the event of a failure of one or two processors and execution continues without interruption. Each processor communicates with its neighboring processors through input/output (I/O) ports which are used as bypass links between the processors. In the event of a processor failure, the function of the faulty processor is assigned to the next processor that is free from faults. The fast Fourier transform (FFT) algorithm is implemented on the simulated circuit to evaluate the performance of the proposed system. The results showed that the system can continue to execute even if one or two processors fail without a noticeable decrease in performance.
Co-Authors Ahmad F. Al-Allaf Mustafa Mohammad Jasim