Article Per Year (5 Year)
p-Index From 2021 - 2026
0.23
P-Index
This Author published in this journals
All Journal International Journal of Electrical and Computer Engineering
Nam-Jin Oh
Korea National University of Transportation
Computer Science & IT Electrical & Electronics Engineering

Published : 2 Documents Claim Missing Document
Claim Missing Document
Check
Articles

Found 2 Documents
Search

 1 
A Single-Stage Quadrature LMVs Nam-Jin Oh
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 1: February 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (674.777 KB) | DOI: 10.11591/ijece.v8i1.pp124-132

Abstract

This paper proposes three kinds of single stage RF front-end, called quadrature LMVs (QLMVs), by merging LNA, single-balanced mixer, and quadrature voltage-controlled oscillator (VCO) exploiting a series LC (SLC) network. The low intermediate frequency (IF) or baseband signal near dc can be directly sensed at the drain nodes of the VCO switching transistors by adding a simple resistor-capacitor (RC) low-pass filter (LPF). Using a 65 nm CMOS technology, the proposed QLMVs are designed. Oscillating at around 2.4 GHz band, the proposed QLMVs achieve the phase noise below ‒107 dB/Hz at 1 MHz offset frequency. The simulated voltage conversion gain is larger than 30 dB. The double-side band (DSB) noise figure (NF) of the proposed QLMVs is below 10 dB. The QLMVs consume less than 0.51 mW dc power from a 1-V supply.
Flicker noise suppression and tuning range linearization techniques for RF CMOS voltage-controlled oscillators Nam-Jin Oh
International Journal of Electrical and Computer Engineering (IJECE) Vol 16, No 4: August 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v16i4.pp1792-1804

Abstract

This paper proposes a differential RF CMOS voltage-controlled oscillator (VCO) employing a series LC (SLC) network to suppress 1/f³ flicker noise and linearize the tuning range. The SLC network incorporates two coupling capacitors connected to each node of a parallel inductor-varactor tank. Each series connection node is cross-coupled to the gates of switching transistors, facilitating a large signal swing. By optimizing the coupling capacitance, 1/f³ flicker noise is effectively mitigated. Designed in 180 nm CMOS technology, the proposed NMOS-only SLC VCO is compared with a conventional differential VCO using a parallel LC (PLC) network. Targeted for 3.3 GHz applications, the VCO maintains a consistent phase noise slope of −20 dB/decade across offset frequencies from 1kHz to 10 MHz. The SLC VCO achieves a phase noise of −71.6 dBc/Hz at a 1 kHz offset and −131.5 dBc/Hz at a 1 MHz offset with a power consumption of 11.9 mW from a 1.5 V supply. The resulting figure of merit (FOM) is 191.3 dBc/Hz at a 1 MHz offset.
Co-Authors