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All Journal International Journal of Electrical and Computer Engineering
Syed Ershad Ahmed
BITS Pilani, Hyderabad Campus
Computer Science & IT Electrical & Electronics Engineering

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Compressor based approximate multiplier architectures for media processing applications Uppugunduru Anil Kumar; Syed Ershad Ahmed
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 4: August 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v11i4.pp2953-2961

Abstract

Approximate computing is an attractive technique to gain substantial improvement in the area, speed, and power in applications where exact computation is not required. This paper proposes two improved multiplier designs based on a new 4:2 approximate compressor circuit to simplify the hardware at the partial product reduction stage. The proposed multiplier designs are targeted towards error-tolerant applications. Exhaustive error and hardware analysis has been carried out on the existing and proposed multiplier designs. The results prove that the proposed approximate multiplier architecture performs better than the existing architectures without significant compromise on quality metrics. Experimental results show that die-area and power consumed are reduced upto 28%, and 25.29% respectively in comparison with the existing designs without significant compromise on accuracy.
Co-Authors Uppugunduru Anil Kumar