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Anand Jatti
R.V. College of Engineering
Computer Science & IT Electrical & Electronics Engineering

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Reconfigurable High Performance Secured NoC Design Using Hierarchical Agent-based Monitoring System Kendaganna Swamy S; Anand Jatti; Uma B. V
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 6: December 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (546.797 KB) | DOI: 10.11591/ijece.v8i6.pp4164-4174

Abstract

With the rapid increase in demand for high performance computing, there is also a significant growth of data communication that leads to leverage the significance of network on chip. This paper proposes a reconfigurable fault tolerant on chip architecture with hierarchical agent based monitoring system for enhancing the performance of network based multiprocessor system on chip against faulty links and nodes. These distributed agents provide healthy status and congestion information of the network. This status information is used for further packet routing in the network with the help of XY routing algorithm. The functionality of Agent is enhanced not only to work as information provider but also to take decision for packet to either pass or stop to the processing element by setting the firewall in order to provide security. Proposed design provides a better performance and area optimization by avoiding deadlock and live lock as compared to existing approaches over network design.
Co-Authors Kendaganna Swamy S Uma B. V