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Stefano Capoccia
University of Salento
Computer Science & IT Electrical & Electronics Engineering

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High-performance AES-128 algorithm implementation by FPGA-based SoC for 5G communications Paolo Visconti; Ramiro Velazquez; Stefano Capoccia; Roberto de Fazio
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 5: October 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v11i5.pp4221-4232

Abstract

In this research work, a fast and lightweight AES-128 cypher based on the Xilinx ZCU102 FPGA board is presented, suitable for 5G communications. In particular, both encryption and decryption algorithms have been developed using a pipelined approach, so enabling the simultaneous processing of the rounds on multiple data packets at each clock cycle. Both the encryption and decryption systems support an operative frequency up to 220 MHz, reaching 28.16 Gbit/s maximum data throughput; besides, the encryption and decryption phases last both only ten clock periods. To guarantee the interoperability of the developed encryption/decryption system with the other sections of the 5G communication apparatus, synchronization and control signals have been integrated. The encryption system uses only 1631 CLBs, whereas the decryption one only 3464 CLBs, ascribable, mainly, to the Inverse Mix Columns step. The developed cypher shows higher efficiency (8.63 Mbps/slice) than similar solutions present in literature.
Co-Authors Paolo Visconti Ramiro Velázquez Roberto De Fazio