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Jagamohan Padhi
Sambalpur University Institute of Information Technology
Computer Science & IT Electrical & Electronics Engineering

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Improved Rejection Penalty Algorithm with Multiprocessor Rejection Technique Prativa Satpathy; Kalyan Das; Jagamohan Padhi
International Journal of Electrical and Computer Engineering (IJECE) Vol 5, No 3: June 2015
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (264.046 KB) | DOI: 10.11591/ijece.v5i3.pp477-482

Abstract

This paper deals with multiprocessor scheduling with rejection technique where each job is provided with processing time and a given penalty cost. If the job satisfies the acceptance condition, it will schedule in the least loaded identical parallel machine else job is rejected. In this way its penalty cost is calculated. Our objective is to minimize the makespan of the scheduled job and to minimize the sum of the penalties of rejected jobs. We have merged ‘CHOOSE ‘and ‘REJECTION PENALTY’ algorithm to reduce the sum of penalties cost and makespan. Our proposed ‘Improved Reject penalty algorithm’ reduce competitive ratio, which in turn enhances the efficiency of the on-line algorithm. By applying our new on-line technique, we got the lower bound of our algorithm is is 1.286 which is far better from the existing algorithms whose competitive ratio is at 1.819. In our approach we have consider non-preemption scheduling technique.
Co-Authors Kalyan Das Prativa Satpathy