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All Journal International Journal of Electrical and Computer Engineering International Journal of Reconfigurable and Embedded Systems (IJRES)
Pradeep Juneja
Graphic Era University
Computer Science & IT Economics, Econometrics & Finance Electrical & Electronics Engineering

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Identifying Appliances using NIALM with Minimum Features Sunil Semwal; R S Prasad; Pradeep Juneja
International Journal of Electrical and Computer Engineering (IJECE) Vol 4, No 6: December 2014
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (374.963 KB)

Abstract

Government of India has decided to install smart meters in fourteen states. Smart meters are required to identify home appliances to fulfill various tasks in the smart grid environment. Both intrusive and non-intrusive methods have been suggested for identification. However, intrusive method is not suitable for cost and privacy reasons. On the other hand, techniques using non-intrusive appliance load monitoring (NIALM) are yet to result in meaningful practical implementation. Two major challenges in NIALM research are the choice of features (load signatures of appliances), and the appropriate algorithm. Both have a direct impact on the cost of the smart meter. In this paper, we address the two issues and propose a procedure with only four features and a simple algorithm to identify appliances. Our experimental setup, on the recommended specifications of the internal electrical wiring in Indian residences, used common household appliances’ load signatures of active and reactive powers, harmonic components and their magnitudes. We show that these four features are essential and sufficient for implementation of NIALM with a simple algorithm. We have introduced a new approach of ‘multi point sensing’ and ‘group control’ rather than the ‘single point sensing’ and ‘individual control’, used so far in NIALM techniques.DOI:http://dx.doi.org/10.11591/ijece.v4i6.6715
Optimization of Resource Utilization of Fast Fourier Transform Subhash Chandra Yadav; Pradeep Juneja; R. G. Varshney
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 3: November 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (477.072 KB) | DOI: 10.11591/ijres.v6.i3.pp186-190

Abstract

This paper considers the optimization of resource utilization for three FFT algorithms, as it pertains not to the input samples or output modes, but to the twiddle factors that arise in Cooley-Tukey FFT algorithms. Twiddle factors are a set of complex roots of unity, fixed by the transform order for the particular algorithm. This paper shows the comparison between three known FFT algorithms, DIT-FFT, DIF-FFT and GT algorithm. All these algorithms are implemented on FPGA (Spartan-3 XC3S4000l-4fg900) with XILINX 10.1 ISE.
Co-Authors R S Prasad R. G. Varshney Subhash Chandra Yadav Sunil Semwal