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P. Manimegalai
Karpagam University, India
Computer Science & IT Electrical & Electronics Engineering

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Current Comparison Domino based CHSK Domino Logic Technique for Rapid Progression and Low Power Alleviation J. Muralidharan; P. Manimegalai
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 5: October 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (68.5 KB) | DOI: 10.11591/ijece.v7i5.pp2468-2473

Abstract

The proposed domino logic is developed with the combination of Current Comparison Domino (CCD) logic and Conditional High Speed Keeper (CHSK) domino logic. In order to improve the performance metrics like power, delay and noise immunity, the redesign of CHSK is proposed with the CCD. The performance improvement is based on the parasitic capacitance, which reduces on the dynamic node for robust and rapid process of the circuit. The proposed domino logic is designed with keeper and without keeper to measure the performance metrics of the circuit. The outcomes of the proposed domino logic are better when compared to the existing domino logic circuits. The simulation of the proposed CHSK based on the CCD logic circuit is carried out in Cadence Virtuoso tool.
Co-Authors J. Muralidharan