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Neelam R. Prakash
PEC University of Technology, Chandigarh, India
Computer Science & IT Electrical & Electronics Engineering

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FPGA Implementation of Higher Order FIR Filter Gurpadam Singh; Neelam R. Prakash
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 4: August 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (708.897 KB) | DOI: 10.11591/ijece.v7i4.pp1874-1881

Abstract

The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of the chip area. This limits the number of processing elements (PE) available on the chip to realize a higher order of filter. A model is developed in the Matlab/Simulink environment to investigate the performance of the desired higher order FIR filter. An equivalent FIR filter representation is designed by the Xilinx FIR Compiler by using the exported FIR filter coefficients. The Xilinx implementation flow is completed with the help of Xilinx ISE 14.5. It is observed how the use of higher order FIR filter impacts the resource utilization of the FPGA and it’s the maximum operating frequency.
Co-Authors Gurpadam Singh