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All Journal International Journal of Advances in Applied Sciences Bulletin of Electrical Engineering and Informatics
Hussain K. khleaf
University of Technology
Earth & Planetary Sciences Electrical & Electronics Engineering Environmental Science Materials Science & Nanotechnology Mathematics Physics

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Second order noise shaping for data-weighted averaging technique to improve sigma-delta DAC performance Ali Kerem Nahar; Ansam Subhi Jaddar; Hussain K. Khleaf; Mohmmed Jawad Mortada Mobarek
International Journal of Advances in Applied Sciences Vol 10, No 1: March 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (814.31 KB) | DOI: 10.11591/ijaas.v10.i1.pp79-87

Abstract

In general, the noise shaping responses, a cyclic second-order response is delivered by the method of data weighted averaging (DWA) in which the output of the digital-to-analog converter (DAC) is restricted to one of two states. DWA works efficiently for rather low levels of quantizing; it begins presenting considerable difficulties when internal levels of quantizing are extended further. Though, each added bit of internal quantizing causes an exponentially increasing in power dissipation, complexity, and size of the DWA logic and the DAC. This gives a controlled second-order response accounting for the mismatch of the elements of DAC. The multi-bit DAC is made up of numerous single-bit DACs having values thereof chosen via a digital encoder. This research presents a discussion of the influence of mismatching between unit elements of the delta-sigma DAC. This results in a constrained second-order response accounting for a mismatch of DAC elements. The results of the simulation showed how the effectiveness of the DWA method in reducing band tones. Furthermore, the DWA method has proved its efficiency in solving the mismatching of DAC unit elements. The noise of the mismatching elements is enhanced by 11 dB at 0.01 with the proposed DWA, thereby enhancing the efficiency of the DAC in comparison to the efficiency of the DAC with no use of the circuit of DWA.
Delta-sigma ADC modulator for multibit data converters using passive adder entrenched second order noise shaping Ali Kareem Nahar; Hussain K. Khleaf
Bulletin of Electrical Engineering and Informatics Vol 10, No 4: August 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v10i4.2934

Abstract

This paper introduces a multi-bit data converters (MDC) modulator of the 2nd order delta-sigma analog-to-digital converter use the passive adder proposed. The noise shaping quantizer can provide feedback that has generated quantization noise and perform additional shaping noise first-order by coupling noise method.Thus, two Integrator's with ring amplifier and the MDC is shaped by noise coupling quantizer know the 2nd-order noise coupled with somewhat of a DAC modulator. At a summing point, the inputs are summed and then filtered with a low pass filter. A cyclic second order response is generated with a data weighted averaging (DWA) technique in which the DACs ' outputs are limited to one of two states in the noise shaping responses. Mainly as a result of the harmonic distortion in circuits of amplifier. Transistor rate is equipped for the fully differential switched condenser integrator used, a comparator and DWA. The modulator with proposed DWA design, almost quarterly improved timing margin. A simulated SNDR of 92dB is obtained at 20 MHz sampling frequency; while a sinusoidal output of 4.112 dBFS is tested at 90µs besides 20 MHz as the bandwidth. The power consumption is 0.33 mW while the voltage of the supply is 1.2V.
Optimizing frequency synthesizer performance based on passive adder entrenched technique for 4G communication systems Hussain K. Khleaf; Ali Kareem Nahar; Ansam S. Jabbar
Bulletin of Electrical Engineering and Informatics Vol 11, No 2: April 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v11i2.3196

Abstract

Noise in 4G communication systems is a pressing current problem. There are various ways to reduce phase noise. The sigma-delta passive adder entrenched (PAE) approach was chosen for the WCDMA system because it provides a spurious level, phase noise, and low stabilization time. Therefore, for WCDMA applications, this study proposes a frequency synthesizer. It is then suggested that the addition of a passive adder before the modulator's quantizer to eradicate any distortions created as a result of the quantization stage. The design factors for the suggested second order synthesizer for 4G are chosen based on the analytical results for all unit of the suggested system and in accordance with WCDMA specifications. The suggested PAE frequency synthesizer for the application of WCDMA reduces noise exact effectively, according to simulation findings. With this synthesizer, the in-band phase noise is -75 dBc/Hz. For frequency synthesizer simulation, MATLAB (R2020) is utilized.
Co-Authors Ali kareem Nahar Ali Kerem Nahar Ansam S. Jabbar Ansam Subhi Jaddar Mohmmed Jawad Mortada Mobarek