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Ali kareem Nahar
University of Technology
Electrical & Electronics Engineering

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Delta-sigma ADC modulator for multibit data converters using passive adder entrenched second order noise shaping Ali Kareem Nahar; Hussain K. Khleaf
Bulletin of Electrical Engineering and Informatics Vol 10, No 4: August 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v10i4.2934

Abstract

This paper introduces a multi-bit data converters (MDC) modulator of the 2nd order delta-sigma analog-to-digital converter use the passive adder proposed. The noise shaping quantizer can provide feedback that has generated quantization noise and perform additional shaping noise first-order by coupling noise method.Thus, two Integrator's with ring amplifier and the MDC is shaped by noise coupling quantizer know the 2nd-order noise coupled with somewhat of a DAC modulator. At a summing point, the inputs are summed and then filtered with a low pass filter. A cyclic second order response is generated with a data weighted averaging (DWA) technique in which the DACs ' outputs are limited to one of two states in the noise shaping responses. Mainly as a result of the harmonic distortion in circuits of amplifier. Transistor rate is equipped for the fully differential switched condenser integrator used, a comparator and DWA. The modulator with proposed DWA design, almost quarterly improved timing margin. A simulated SNDR of 92dB is obtained at 20 MHz sampling frequency; while a sinusoidal output of 4.112 dBFS is tested at 90µs besides 20 MHz as the bandwidth. The power consumption is 0.33 mW while the voltage of the supply is 1.2V.
Optimizing frequency synthesizer performance based on passive adder entrenched technique for 4G communication systems Hussain K. Khleaf; Ali Kareem Nahar; Ansam S. Jabbar
Bulletin of Electrical Engineering and Informatics Vol 11, No 2: April 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v11i2.3196

Abstract

Noise in 4G communication systems is a pressing current problem. There are various ways to reduce phase noise. The sigma-delta passive adder entrenched (PAE) approach was chosen for the WCDMA system because it provides a spurious level, phase noise, and low stabilization time. Therefore, for WCDMA applications, this study proposes a frequency synthesizer. It is then suggested that the addition of a passive adder before the modulator's quantizer to eradicate any distortions created as a result of the quantization stage. The design factors for the suggested second order synthesizer for 4G are chosen based on the analytical results for all unit of the suggested system and in accordance with WCDMA specifications. The suggested PAE frequency synthesizer for the application of WCDMA reduces noise exact effectively, according to simulation findings. With this synthesizer, the in-band phase noise is -75 dBc/Hz. For frequency synthesizer simulation, MATLAB (R2020) is utilized.
Co-Authors Ansam S. Jabbar Hussain K. khleaf