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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Subhash Kulkarni
PESIT-Bangalore South Campus
Economics, Econometrics & Finance

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Enhanced MAC controller architecture for 2D processing based on FPGA with configurable resource allocation Chiranjeevi G. N.; Subhash Kulkarni
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 3: November 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v10.i3.pp212-220

Abstract

The bulks of image processing algorithms are either two-dimensional (2D) or confined by their very nature. As a result, the 2D convolution function has a large impact on picture processing requirements. The methodology of 2D convolution and media access control (MAC) design can also be used to perform a variety of image processing tasks, and even as picture blurring, softening, and feature extraction. The main goal of this research is to develop a more efficient MAC control block-based 2D convolution architecture. This 2D algorithm can be implemented in hardware using fewer modules, multipliers, adders, and control blocks, resulting in significant hardware savings and look up table (LUT) reductions. The simulations were run in Verilog, and the Xilinx Vertex family field programmable gate array (FPGA) was used to build and test them. The recommended 2D convolution architectural solution is significantly faster and consumes significantly less hardware resources than the traditional 2D convolution implementation. The proposed architecture will result in technology that saves a substantial amount of processing time when it comes to LUTs.
Image processing using a reconfigurable platform: Pre-processing block hardware architecture Chiranjeevi G. N.; Subhash Kulkarni
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 3: November 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v10.i3.pp230-236

Abstract

Real time image processing is a challenging task in which fetching the sub image requires offset memory access apart from core processing needs. This paper aims at overcoming the offset needs for memory addressing in pre-processing blocks. Another feature of this present work is to appending the image data with customized algorithmic reequipments viz duplicating, zero padding. For KxK kernel size, the proposed hardware architecture can be programmed to fetch K pixels in one cycle, reducing the data access time. Results have been compared with software-based processing for KxK spatial filtering. performance indicates significant timing improvement using proposed pre-processing hardware block.
Co-Authors Chiranjeevi G. N.