Article Per Year (5 Year)
p-Index From 2020 - 2025
0.444
P-Index
This Author published in this journals
All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Tirumale Ramesh
Jackson State University
Economics, Econometrics & Finance

Published : 2 Documents Claim Missing Document
Claim Missing Document
Check
Articles

Found 2 Documents
Search

 1 
Cost-efficient reconfigurable geometrical bus interconnection system for many-core platforms Tirumale Ramesh; Khalid Abed
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 2: July 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v10.i2.pp77-89

Abstract

System-on-chip (SoC) embedded computing platforms can support a wide range of next generation embedded artificial intelligence and other computationally intensive applications. These platforms require cost effective interconnection network. Network-on-chip has been widely used today for on-chip interconnection. However, it is still considered expensive for large system sizes. As full bus-based interconnection has high number of bus connections, reduced bus connections might offer considerable implementation economies with relatively small design cost for field programmable gate arrays (FPGAs) based embedded platforms. In this paper, we propose a cost efficient generalized reconfigurable bus-based interconnection for many-core system with reduced number of bus connections. We generalize the system with b =min {n,m}/k number of interconnect buses in which where n is the number of processor cores, m is the number of memory-modules and k is the general bus reduction factor. We present four geometrical interconnect configurations and provide their characterization in terms of memory bandwidth, cost per bandwidth and bus fault tolerance for various system sizes. Our results show that these configurations provide reduced cost per bandwidth and can achieve higher system throughput with bus cache.
An efficient multi-level cache system for geometrically interconnected many-core chip multiprocessor Tirumale Ramesh; Khalid H Abed
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 11, No 1: March 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v11.i1.pp93-102

Abstract

Many-core chip multiprocessor offers high parallel processing power for big data analytics; however, they require efficient multi-level cache and interconnection to achieve high system throughput. Using on-chip first level L1 and second level L2 per core fast private caches is expensive for large number of cores. In this paper, for moderate number of cores from 16 to 64, we present a cost and performance efficient multi-level cache system with per core L1 and last level shared bus cache on each bus line of a cost-efficient geometrically bus-based interconnection. In our approach, we extracted cache hit and miss concurrencies and applied concurrent average memory access time to more accurately determine the cache system performance. We conducted least recently used cache policy-based simulation for cache system with L1, with L1/L2, and with L1/shared bus cache. Our simulation results show that an average system throughput improvement of 2.5x can be achieved by using system with L1/shared bus cache system compared to using only first level L1 or L1/L2. Further, we show that the throughput degradation for the proposed cache system is only within 5% for a single bus fault, suggesting a good bus fault tolerance.
Co-Authors Khalid Abed Khalid H Abed